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960
nstruction code
1st byte
2nd byte
AH
AL
BH
BL
3rd byte
4th byte
CH
CL
DH
DL
r is the register specification field.
aa is the absolute address specification.
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Notes:
AH AL BH BL CH
CL
01C05
01D05
01F06
7Cr06
*
1
7Cr07
*
1
7Dr06
*
1
7Dr07
*
1
7Eaa6
*
2
7Eaa7
*
2
7Faa6
*
2
7Faa7
*
2
0
MULXS
BSET
BSET
BSET
BSET
1
DIVXS
BNOT
BNOT
BNOT
BNOT
2
MULXS
BCLR
BCLR
BCLR
BCLR
3
DIVXS
BTST
BTST
BTST
BTST
4
OR
5
XOR
6
AND
789
A
B
C
D
E
F
1.
2.
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Table A-3 Operation Code Map (3)
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...