61
(c) Interrupt control mode 0
(d) Interrupt control mode 2
CCR
PC
(24 bits)
SP
CCR
PC
(24 bits)
SP
EXR
Reserved
*
1
(a) Interrupt control mode 0
(b) Interrupt control mode 2
CCR
CCR
*
1
PC
(16 bits)
SP
CCR
CCR
*
1
PC
(16 bits)
SP
EXR
Reserved
*
1
Normal mode
*
2
Advanced mode
Notes: 1. Ignored when returning.
2. Not available in the H8S/2633 Series.
Figure 2-16 Stack Structure after Exception Handling (Examples)
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...