873
24.6.5
Usage Notes
I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1,
the address bus and bus control signal output is also retained. Therefore, there is no reduction in
current dissipation for the output current when a high-level signal is output.
Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation
increases during the oscillation stabilization wait period.
Write Data Buffer Function: The write data buffer function and software standby mode cannot
be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL
should be cleared to 0 to cancel the write data buffer function before entering software standby
mode. Also check that external writes have finished, by reading external addresses, etc., before
executing a SLEEP instruction to enter software standby mode. See section 7.9, Write Data Buffer
Function, for details of the write data buffer function.
24.7
Hardware Standby Mode
24.7.1
Hardware Standby Mode
When the
STBY
pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the
STBY
pin low.
Do not change the state of the mode pins (MD2 to MD0) while the H8S/2633 Series is in hardware
standby mode.
Hardware standby mode is cleared by means of the
STBY
pin and the
RES
pin. When the
STBY
pin is driven high while the
RES
pin is low, the reset state is set and clock oscillation is started.
Ensure that the
RES
pin is held low until the clock oscillator stabilizes (at least 8 ms—the
oscillation stabilization time—when using a crystal oscillator). When the
RES
pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...