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8.1.5
Register Configuration
Table 8-3 summarizes the DMAC registers.
Table 8-3
DMAC Registers
Channel Name
Abbreviation R/W
Initial
Value
Address
*
Bus Width
0
Memory address register 0A
MAR0A
R/W
Undefined H'FEE0
16 bits
I/O address register 0A
IOAR0A
R/W
Undefined H'FEE4
16 bits
Transfer count register 0A
ETCR0A
R/W
Undefined H'FEE6
16 bits
Memory address register 0B
MAR0B
R/W
Undefined H'FEE8
16 bits
I/O address register 0B
IOAR0B
R/W
Undefined H'FEEC
16 bits
Transfer count register 0B
ETCR0B
R/W
Undefined H'FEEE
16 bits
1
Memory address register 1A
MAR1A
R/W
Undefined H'FEF0
16 bits
I/O address register 1A
IOAR1A
R/W
Undefined H'FEF4
16 bits
Transfer count register 1A
ETCR1A
R/W
Undefined H'FEF6
16 bits
Memory address register 1B
MAR1B
R/W
Undefined H'FEF8
16 bits
I/O address register 1B
IOAR1B
R/W
Undefined H'FEFC
16 bits
Transfer count register 1B
ETCR1B
R/W
Undefined H'FEFE
16 bits
0, 1
DMA write enable register
DMAWER
R/W
H'00
H'FF60
8 bits
DMA terminal control register
DMATCR
R/W
H'00
H'FF61
8 bits
DMA control register 0A
DMACR0A
R/W
H'00
H'FF62
16 bits
DMA control register 0B
DMACR0B
R/W
H'00
H'FF63
16 bits
DMA control register 1A
DMACR1A
R/W
H'00
H'FF64
16 bits
DMA control register 1B
DMACR1B
R/W
H'00
H'FF65
16 bits
DMA band control register
DMABCR
R/W
H'0000
H'FF66
16 bits
Module stop control register A MSTPCRA
R/W
H'3F
H'FDE8
8 bits
Note:
*
Lower 16 bits of the address.
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...