579
ø
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
Figure 15-6 Timing of Setting of OVF
15.3.4
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At
the same time, the
WDTOVF
signal goes low. If TCNT overflows while the RSTE bit in RSTCSR
is set to 1, an internal reset signal is generated for the entire H8S/2633 Series chip. Figure 15-7
shows the timing in this case.
ø
TCNT
H'FF
H'00
Overflow signal
(internal signal)
WOVF
WDTOVF signal
Internal reset
signal
132 states
518 states (WDT0)
515/516 states (WDT1)
Figure 15-7 Timing of Setting of WOVF
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...