498
12.1.4
Registers
Table 12-2 summarizes the PPG registers.
Table 12-2 PPG Registers
Name
Abbreviation
R/W
Initial Value
Address
*
1
PPG output control register
PCR
R/W
H'FF
H'FE26
PPG output mode register
PMR
R/W
H'F0
H'FE27
Next data enable register H
NDERH
R/W
H'00
H'FE28
Next data enable register L
*
4
NDERL
R/W
H'00
H'FE29
Output data register H
PODRH
R/(W)
*
2
H'00
H'FE2A
Output data register L
PODRL
R/(W)
*
2
H'00
H'FE2B
Next data register H
NDRH
R/W
H'00
H'FE2C
*
3
H'FE2E
Next data register L
*
4
NDRL
R/W
H'00
H'FE2D
*
3
H'FE2F
Port 1 data direction register
P1DDR
W
H'00
H'FE30
Module stop control register A
MSTPCRA
R/W
H'3F
H'FDE8
Notes: 1. Lower 16 bits of the address.
2. A bit that has been set for pulse output by NDER is read-only.
3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FE2C. When the output triggers are different, the
NDRH address is H'FE2E for group 2 and H'FE2C for group 3.
Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by
the PCR setting, the NDRL address is H'FE2D. When the output triggers are different,
the NDRL address is H'FE2F for group 0 and H'FE2D for group 1.
4. The H8S/2633 Series has no pins corresponding to pulse output groups 0 and 1.
Содержание H8S/2631
Страница 28: ...xviii Appendix G Package Dimensions 1154 ...
Страница 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...
Страница 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...
Страница 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...