Hitachi H8S/2631, Руководство по оборудованию

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Table 9-9 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM On-
Chip
ROM
On-Chip I/O
Registers
External Devices
Bus width 32 16 8 16 8 16
Access states 1 1 2 2 2 3 2 3
Execution Vector read S
I
— 1 — — 4 6+2m 2 3+m
status
Register
information
read/write S
J
1 — — — — — — —
Byte data read S
K
1 1 2 2 2 3+m 2 3+m
Word data read S
K
1 1 4 2 4 6+2m 2 3+m
Byte data write S
L
1 1 2 2 2 3+m 2 3+m
Word data write S
L
1 1 4 2 4 6+2m 2 3+m
Internal operation S
M
1
The number of execution states is calculated from the formula below. Note that
Σ
means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+
Σ
(J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.