GD32F10x User Manual
392
Counter auto reload register (TIMERx_CAR)
Address offset: 0x2C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CARL[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
CARL[15:0]
Counter auto reload value
This bit-filed specifies the auto reload value of the counter.
Note: When the timer is configured in input capture mode, this register must be
configured a non-zero value (such as 0xFFFF) which is larger than user expected
value.
Channel 0 capture/compare value register (TIMERx_CH0CV)
Address offset: 0x34
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH0VAL[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
CH0VAL[15:0]
Capture or compare value of channel0
When channel 0 is configured in input mode, this bit-filed indicates the counter value
corresponding to the last capture event. And this bit-filed is read-only.
When channel 0 is configured in output mode, this bit-filed contains value to be
compared to the counter. When the corresponding shadow register is enabled, the
Содержание GD32F10 Series
Страница 1: ...GigaDevice Semiconductor Inc GD32F10x Arm Cortex M3 32 bit MCU User Manual Revision 2 6 Jun 2022 ...
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Страница 416: ...GD32F10x User Manual 416 shadow register updates every update event ...
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Страница 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...