GigaDevice Semiconductor GD32F10 Series, Руководство пользователя

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GD32F10x User Manual
88
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
ADCPSC[
2]
PLLMF[4] CKOUT0SEL[2:0] USBDPSC[1:0] PLLMF[3:0] PREDV0 PLLSEL
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0]
rw rw rw rw r rw
Bits Fields Descriptions
31:29 Reserved Must be kept at reset value.
28 ADCPSC[2] Bit 2 of ADCPSC
see bits 15:14 of RCU_CFG0
27 PLLMF[4] Bit 4 of PLLMF
see bits 21:18 of RCU_CFG0
26:24 CKOUT0SEL[2:0] CKOUT0 clock source selection
Set and reset by software.
0xx: No clock selected
100: System clock selected
101: Internel 8MHz RC Oscillator clock selected
110: External high speed oscillator clock selected
111: (CK_PLL / 2) clock selected
23:22 USBDPSC[1:0] USBD clock prescaler selection
Set and reset by software to control the USBD clock prescaler value. The USBD
clock must be 48MHz. These bits can’t be reset if the USBD clock is enabled.
00: CK_USBD = CK_PLL / 1.5
01: CK_USBD = CK_PLL
10: CK_USBD = CK_PLL / 2.5
11: CK_USBD = CK_PLL / 2
21:18 PLLMF[3:0] The PLL clock multiplication factor
Bit 27 of RCU_CFG0 and these bits are written by software to define the PLL
multiplication factor.
Note : The PLL output frequency must not exceed 108 MHz
00000: CK_SYS = CK_PLL x 2
00001: CK_SYS = CK_PLL x 3
00010: CK_SYS = CK_PLL x 4
00011: CK_SYS = CK_PLL x 5
00100: CK_SYS = CK_PLL x 6
00101: CK_SYS = CK_PLL x 7
00110: CK_SYS = CK_PLL x 8