GigaDevice Semiconductor GD32F10 Series, Руководство пользователя

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GD32F10x User Manual
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transmission packet. All IN channels shares the Rx FIFO for packets reception. All the
periodic OUT channels share the periodic Tx FIFO to packets tramsmission. All the non-
periodic OUT channels share the non-Periodic FIFO for transmit packets. The size and start
offset of these data FIFOs should be configured using these registers: USBFS_GRFLEN,
USBFS_HNPTFLEN and USBFS_HPTFLEN. Figure 24-5. HOST mode FIFO space in
SRAM describes the structure of these FIFOs in SRAM. The values in the figure are in term
of 32-bit words.
Figure 24-5. HOST mode FIFO space in SRAM
Rx FIFO
Rx FIFO
Non-Periodic Tx FIFO
Periodic Tx FIFO
HNPTXRSAR[15:0]
HNPTXFD
HPTXFD
HPTXRSAR[15:0]
RXFD
Start: 0x00
End: 0x13F
USBFS provides a special register area for the internal data FIFO reading and writing. Figure
24-6. Host mode FIFO access register map describes the register memory area that the
data FIFO can access.The addresses in the figure are addressed in bytes. Each channel has
its own FIFO access register space, although all Non-periodic channels share the same FIFO
and all the Periodic channels also share the same FIFO. It is important for USBFS to know
which channel the current pushed packet belongs to. Rx FIFO is also able to be accessed by
using USBFS_GRSTATR/ USBFS_GRSTATP register.
Figure 24-6. Host mode FIFO access register map
CH0 FIFO Write/Read
CH1 FIFO Write/Read
1000h-1FFFh
CH7 FIFO Write/Read
...
2000h-2FFFh
8000h-8FFFh
Device mode
In device mode, the data FIFO is divided into several parts: one Rx FIFO, and 4 Tx FIFOs
(one for each IN endpoint). All the OUT endpoints share the Rx FIFO for receiving packets.
The size and start offset of these data FIFOs should be configured by using USBFS_GRFLEN
and USBFS_DIEPxTFLEN (x=0
…3) registers.
Figure 24-7. Device mode FIFO space in
SRAM describes the structure of these FIFOs in SRAM. The values in the figure are in term