GigaDevice Semiconductor GD32F10 Series, Руководство пользователя

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GD32F10x User Manual
141
0: No reset
1: Reset the USBFS
11:0 Reserved Must be kept at reset value
5.6.12.
Clock configuration register 1 (RCU_CFG1)
Address offset: 0x2C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved I2S2SEL I2S1SEL
PREDV0
SEL
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL2MF[3:0] PLL1MF[3:0] PREDV1[3:0] PREDV0[3:0]
rw rw rw rw
Bits Fields Descriptions
31:19 Reserved Must be kept at reset value
18 I2S2SEL I2S2 clock source selection
Set and reset by software to control the I2S2 clock source.
0: System clock selected as I2S2 source clock
1: (CK_PLL2 x 2) selected as I2S2 source clock
17 I2S1SEL I2S1 clock source selection
Set and reset by software to control the I2S1 clock source.
0: System clock selected as I2S1 source clock
1: (CK_PLL2 x 2) selected as I2S1 source clock
16 PREDV0SEL PREDV0 input clock source selection
Set and reset by software.
0: HXTAL selected as PREDV0 input source clock
1: CK_PLL1 selected as PREDV0 input source clock
15:12 PLL2MF[3:0] The PLL2 clock multiplication factor
Set and reset by software.
00xx: reserve
010x: reserve
0110: (PLL2 source clock x 8)
0111: (PLL2 source clock x 9)
1000 :(PLL2 source clock x 10)
1001: (PLL2 source clock x 11)
1010: (PLL2 source clock x 12)