GigaDevice Semiconductor GD32F10 Series, Руководство пользователя

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GD32F10x User Manual
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domain control register (RCU_BDCTL). The LXTALSTB flag in the backup domain control
register (RCU_BDCTL) will indicate if the LXTAL clock is stable. An interrupt can be
generated if the related interrupt enable bit, LXTALSTBIE, in the interrupt register RCU_INT
is set when the LXTAL becomes stable.
Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the backup
Domain control register (RCU_BDCTL). The CK_LXTAL is equal to the external clock which
drives the OSC32IN pin.
Internal 40K RC oscillator (IRC40K)
The internal RC oscillator has a frequency of about 40 kHz and is a low power clock source
for the real time clock circuit or the free watchdog timer. The IRC40K offers a low cost clock
source as no external components are required. The IRC40K RC oscillator can be switched
on or off by using the IRC40KEN bit in the Reset source/clock Register (RCU_RSTSCK). The
IRC40KSTB flag in the reset source/clock register RCU_RSTSCK will indicate if the IRC40K
clock is stable. An interrupt can be generated if the related interrupt enable bit IRC40KSTBIE
in the Clock Interrupt Register (RCU_INT) is set when the IRC40K becomes stable.
The IRC40K can be trimmed by TIMER4_CH3, user can get the clocks frequency, and adjust
the RTC and FWDGT counter. Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register.
System clock (CK_SYS) selection
After the system reset, the default CK_SYS source will be IRC8M and can be switched to
HXTAL or CK_PLL by changing the system clock switch bits, SCS, in the clock configuration
register 0, RCU_CFG0. When the SCS value is changed, the CK_SYS will continue to
operate using the original clock source until the target clock source is stable. When a clock
source is directly or indirectly (by PLL) used as the CK_SYS, it is not possible to stop it.
HXTAL clock monitor (CKM)
The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit, CKMEN,
in the control register (RCU_CTL). This function should be enabled after the HXTAL start-up
delay and disabled when the HXTAL is stopped. Once the HXTAL failure is detected, the
HXTAL will be automatically disabled. The HXTAL clock Stuck interrupt Flag, CKMIF, in the
clock Interrupt Register, RCU_INT, will be set and the HXTAL failure event will be generated.
This failure interrupt is connected to the non-maskable interrupt, NMI, of the Cortex-M3. If the
HXTAL is selected as the clock source of CK_SYS, PLL and CK_RTC, the HXTAL failure will
force the CK_SYS source to IRC8M, the PLL will be disabled automatically. If the HXTAL is
selected as the clock source of PLL, the HXTAL failure will force the PLL closed automatically.
If the HXTAL is selected as the clock source of RTC, the HXTAL failure will reset the RTC
clock selection.