GD32F10x User Manual
341
Table 15-9. Ouput trigger of Timerx(x=1,2,3,4)
TIMER1_TRGO
TIMER2_TRGO
TIMER3_TRGO
TIMER4_TRGO
TIMER0
ITI1
ITI2
ITI3
ITI0
TIMER1
-
ITI2
ITI3
-
TIMER2
ITI1
-
ITI3
ITI2
TIMER3
ITI1
ITI2
-
-
TIMER4
ITI0
ITI1
ITI2
TIMER7
ITI1
-
ITI2
ITI3
TIMER8
ITI0
ITI1
-
-
TIMER11
-
-
ITI0
ITI1
Note:
‘-’ means no interconnection.
Other example can refer to
Advanced timer (TIMERx, x=0, 7)
..
Timer DMA mode
Timer’s DMA mode is the function that configures timer’s register by DMA module. The
relative registers are TIMERx_DMACFG and TIMERx_DMATB; Of course, you have to
enable a DMA request which will be asserted by some internal interrupt event. When the
interrupt event was asserted, TIMERx will send a request to DMA, which is configured to M2P
mode and PADDR is TIMERx_DMATB, then DMA will access the TIMERx_DMATB. In fact,
register TIMERx_DMATB is only a buffer; timer will map the TIMERx_DMATB to an internal
register, appointed by the field of DMATA in TIMERx_DMACFG. If the field of DMATC in
TIMERx_DMACFG
is 0(1 transfer), then the timer’s DMA request is finished. While if
TIMERx_DMATC is not 0, such as 3( 4 transfers), then timer will send 3 more requests to
DMA, and DMA will access timer’s registers 0x4, 0x8, 0xc
at the next 3 accesses to TIMERx_DMATB. In one word, one time DMA internal interrupt
event assert, DMATC+1 times request will be send by TIMERx.
If one more time DMA request event coming, TIMERx will repeat the process as above.
Timer debug mode
When the Cortex
®
-M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL register
set to 1, the TIMERx counter stops.
Содержание GD32F10 Series
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Страница 416: ...GD32F10x User Manual 416 shadow register updates every update event ...
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Страница 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...