71
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Notes:
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other
than interrupts. The IPSR returns the Exception number, see
“Interrupt Program Status Register”
for more information
“System Handler Priority Registers”
“Interrupt Priority Registers”
5. Increasing in steps of 4.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that
shows as having configurable pri-
ority, see:
•
“System Handler Control and State Register”
•
“Interrupt Clear-enable Registers”
For more information about hard faults, memory management faults, bus faults, and usage
faults, see
11.4.3.3
Exception Handlers
The processor handles exceptions using:
• Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs.
• Fault Handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by
the fault handlers.
• System Handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are
handled by system handlers.
4 -12
Memory
management fault
Configurable
0x00000010
Synchronous
5
-11
Bus fault
Configurable
0x00000014
Synchronous when
precise, asynchronous
when imprecise
6
-10
Usage fault
Configurable
0x00000018
Synchronous
7-10
-
-
-
Reserved
-
11
-5
SVCall
Configurable
0x0000002C
Synchronous
12-13
-
-
-
Reserved
-
14
-2
PendSV
Configurable
0x00000038
Asynchronous
15
-1
SysTick
Configurable
0x0000003C Asynchronous
16 and above
0 and above
Interrupt (IRQ)
Configurable
0x00000040 and
above
Asynchronous
Table 11-9.
Properties of the Different Exception Types (Continued)
Exception
Number
(1)
Irq Number
(1)
Exception Type
Priority
Vector Address
or Offset
(2)
Activation
Summary of Contents for SAM4S Series
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