Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Notes: 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with
ICI continuation.
Fault Escalation and Hard Faults
All faults exceptions except for hard fault have configurable exception priority, see “System Han-
dler Priority Registers” . The software can disable the execution of the handlers for these faults,
see “System Handler Control and State Register” .
Usually, the exception priority, together with the values of the exception mask registers, deter-
mines whether the processor enters the fault handler, and whether a fault handler can preempt
another fault handler, as described in
“Exception Model” .
In some situations, a fault with configurable priority is treated as a hard fault. This is called prior-
ity escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself; it must have the same priority as
the current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is
because the handler for the new fault cannot preempt the currently executing fault handler.
• An exception handler causes a fault for which the priority is the same as or lower than the
currently executing exception.
MPU or default memory map mismatch:
Memory
management
fault
- -
on instruction access IACCVIOL
“MMFSR: Memory Management Fault
Status Subregister”
on data access DACCVIOL
(2)
during exception stacking MSTKERR
during exception unstacking MUNSKERR
during lazy floating-point state preservation MLSPERR
Bus error:
Bus fault
- -
during exception stacking STKERR
“BFSR: Bus Fault Status Subregister”
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
during lazy floating-point state preservation LSPERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
Attempt to access a coprocessor
Usage fault
NOCP
“UFSR: Usage Fault Status Subregister”
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction set state
(1)
INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO
Table 11-11. Faults (Continued)
Fault Handler Bit Name Fault Status Register