Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
21.4 Functional Description
21.4.1 Cache Operation
On reset, the cache controller data entries are all invalidated and the cache is disabled. The
cache is transparent to processor operations. The cache controller is activated through the use
of its configuration registers. The configuration interface is memory mapped in the private
peripheral bus.
Use the following sequence to enable the cache controller.
1. Verify that the cache controller is disabled, reading the value of the CSTS (cache sta-
tus) field of the CMCC_SR register.
2. Enable the cache controller, writing one to CEN (cache enable) field of the
CMCC_CTRL register.
21.4.2 Cache Maintenance
If the contents seen by the cache has changed, the user needs to invalidate the cache entries. It
can be done line by line or for all cache entries.
21.4.2.1 Cache Invalidate by Line Operation
When an invalidate by line command is issued the cache controller resets the valid bit informa-
tion of the decoded cache line. As the line is no longer valid the replacement counter points to
that line.
Use the following sequence to invalidate one line of cache.
1. Disable the cache controller, writing 0 to the CEN field of the CMCC_CTRL register.
2. Check CSTS field of the CMCC_SR to verify that the cache is successfully disabled.
3. Perform an invalidate by line writing the bit set {index, way} in the CMCC_MAINT1
register.
4. Enable the cache controller, writing 1 to the CEN field of the CMCC_CTRL register.
21.4.2.2 Cache Invalidate All Operation
To invalidate all cache entries:
Write 1 to the INVALL field of the CMCC_MAINT0 register.
21.4.3 Cache Performance Monitoring
The Cortex M cache controller includes a programmable 32-bit monitor counter. The monitor can
be configured to count the number of clock cycles, the number of data hits or the number of
instruction hits.
Use the following sequence to activate the counter
1. Configure the monitor counter, writing the MODE field of the CMCC_CFG register.
2. Enable the counter, writing one to the MENABLE field of the CMCC_MEN register.
3. If required, reset the counter, writing one to the SWRST field of the CMCC_MCTRL
register.
4. Check the value of the monitor counter, reading EVENT_CNT field of the CMCC_SR.