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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
11.5
Power Management
The Cortex-M4 processor
sleep modes reduce the power consumption:
• Sleep mode stops the processor clock
• Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see
.
This section describes the mechanisms for entering sleep mode, and the conditions for waking
up from sleep mode.
11.5.1
Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the
processor. Therefore, the software must be able to put the processor back into sleep mode after
such an event. A program might have an idle loop to put the processor back to sleep mode.
11.5.1.1
Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the proces-
sor executes a WFI instruction it stops executing instructions and enters sleep mode. See
for more information.
11.5.1.2
Wait For Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an
one-bit event register. When the processor executes a WFE instruction, it checks this register:
• if the register is 0, the processor stops executing instructions and enters sleep mode
• if the register is 1, the processor clears the register to 0 and continues executing instructions
without entering sleep mode.
for more information.
11.5.1.3
Sleep-On-Exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of
an exception handler, it returns to Thread mode and immediately enters sleep mode. Use this
mechanism in applications that only require the processor to run when an exception occurs.
11.5.2
Wakeup From Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter
sleep mode.
11.5.2.1
Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to
cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this, set the PRIMASK bit to 1
and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than
the current exception priority, the processor wakes up but does not execute the interrupt handler
until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULT-
MASK, see
.
Summary of Contents for SAM4S Series
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