Atmel SAM4S Series, Preliminary Data Sheet

Page: 913 / 1163

913
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
If the waveform is center aligned, then:
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
Figure 37-4. Non Overlapped Center Aligned Waveforms
Note: 1. See Figure 37-5 on page 914 for a detailed description of center aligned waveforms.
When center aligned, the channel counter increases up to CPRD and decreases down to 0. This
ends the period.
When left aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a
left aligned channel.
Waveforms are fixed at 0 when:
• CDTY = CPRD and CPOL = 0
• CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
• CDTY = 0 and CPOL = 0
• CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the
channel output level.
Modifying CPOL in “PWM Channel Mode Register” on page 970 while the channel is enabled
can lead to an unexpected behavior of the device being driven by PWM.
Besides generating output signals OCx, the comparator generates interrupts in function of the
counter value. When the output waveform is left aligned, the interrupt occurs at the end of the
counter period. When the output waveform is center aligned, the bit CES of the PWM_CMRx
register defines when the channel counter interrupt occurs. If CES is set to 0, the interrupt
duty cycle
period 1 fchannel_x_clock CDTY
× ⁄
–
( )
period
------------------------------------------------------------------------------------------------------------ =
duty cycle
period
2
⁄ ( )
1 fchannel_x_clock
CDTY
× ⁄
–
( ) )
period 2
⁄ ( )
------------------------------------------------------------------------------------------------------------------------------ =
OC0
OC1
Period
No overlap