Atmel SAM4S Series, Preliminary Data Sheet

Page: 445 / 1163

445
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 25-29. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Figure 25-30. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
Clock Mode
A[23:0]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
1 1 1 2
3
2
NWE_CYCLE = 7
NORMAL MODE WRITE
Slow clock mode
transition is detected:
Reload Configuration Wait State
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
SLOW CLOCK MODE WRITE
A[23:0]
NCS
1
MCK
NWE
1 1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
2
3
2
NORMAL MODE WRITE IDLE STATE
Reload Configuration
Wait State