Atmel SAM4S Series, Preliminary Data Sheet

Page: 905 / 1163

905
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
37. Pulse Width Modulation Controller (PWM)
37.1 Description
The Pulse Width Modulation Controller (PWM) macrocell controls 4 channels independently.
Each channel controls two complementary square output waveforms. Characteristics of the out-
put waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or
non-overlapping times) are configured through the user interface. Each channel selects and
uses one of the clocks provided by the clock generator. The clock generator provides several
clocks resulting from the division of the PWM master clock (MCK).
All PWM macrocell accesses are made through registers mapped on the peripheral bus. All
channels integrate a double buffering system in order to
prevent an unexpected output wave-
form while modifying the period, the duty-cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle
or dead-times at the same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA
Controller Channel (PDC) which offers buffer transfer without processor Intervention.
The PWM macrocell provides 8 independent comparison units capable of comparing a pro-
grammed value to the counter of the synchronous channels (counter of channel 0). These
comparisons are intended to generate software interrupts, to trigger pulses on the 2 indepen-
dent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of
the PWM outputs) and to trigger PDC transfer requests.
The PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM block provides a fault protection mechanism with 6 fault inputs
, cap
able of detecting a
fault condition and to override the PWM outputs asynchronously (outputs forced to 0, 1).
For safety usage, some configuration registers are write-protected.
37.2 Embedded Characteristics
• One Four-channel 16-bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
• Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
channel
– Independent Enable Disable Commands