Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
25.8 Standard Read and Write Protocols
In the following sections, NCS represents one of the NCS[0..3] chip select lines.
25.8.1 Read Waveforms
The read cycle is shown on Figure 25-5 .
The read cycle starts with the address setting on the memory address bus.
Figure 25-5. Standard Read Cycle
25.8.1.1 NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
falling edge;
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
rising edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
rising edge.
25.8.1.2 NCS Waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before
the NCS falling edge.
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and
NCS rising edge;
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the
NCS rising edge.
A[23:0]
NCS
NRD_SETUP NRD_PULSE NRD_HOLD
MCK
NRD
D[7:0]
NCS_RD_SETUP
NCS_RD_PULSE
NCS_RD_HOLD
NRD_CYCLE