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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
11.6.3.5
Address Alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word,
or multiple word access, or where a halfword-aligned address is used for a halfword access.
Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
• LDR, LDRT
• LDRH, LDRHT
• LDRSH, LDRSHT
• STR, STRT
• STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an
unaligned access, and therefore their accesses must be address-aligned. For more information
about usage faults, see
Unaligned accesses are usually slower than aligned accesses. In addition, some memory
regions might not support unaligned accesses. Therefore, ARM recommends that programmers
ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use
the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses,
see
“Configuration and Control Register”
11.6.3.6
PC-relative Expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or lit-
eral data. It is represented in the instruction as the PC value plus or minus a numeric offset. The
assembler calculates the required offset from the label and the address of the current instruc-
tion. If the offset is too big, the assembler produces an error.
• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current
instruction plus 4 bytes.
• For all other instructions that use labels, the value of the PC is the address of the current
instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus
or minus a number, or an expression of the form [PC, #number].
11.6.3.7
Conditional Execution
Most data processing instructions can optionally update the condition flags in the Application
Program Status Register (APSR) according to the result of the operation, see
. Some instructions update all flags, and some only update a subset. If a
flag is not updated, the original value is preserved. See the instruction descriptions for the flags
they affect.
An instruction can be executed conditionally, based on the condition flags set in another instruc-
tion, either:
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code
suffixes to instructions. See
for a list of the suffixes to add to instructions to make
them conditional instructions. The condition code suffix enables the processor to test a condition
based on the flags. If the condition test of a conditional instruction fails, the instruction:
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