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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
The other lines are configured in Falling Edge or Low Level detection by default, if they have not
been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low
Level detection by writing 32’h0000_004A in PIO_FELLSR.
Figure 29-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
29.5.11
I/O Lines Lock
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller
PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER,
PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and
PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line
is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.
29.5.12
Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is
active. Disabling the Schmitt Trigger is requested when using the QTouch
™
Library.
29.5.13
Parallel Capture Mode
29.5.13.1
Overview
The PIO Controller integrates an interface able to read data from a CMOS digital image sensor,
a high-speed parallel ADC, a DSP synchronous port in synchronous mode, etc.... For better
understanding and to ease reading, the following description uses an example with a CMOS dig-
ital image sensor.
29.5.13.2
Functional Description
The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the
sensor clock, and two data enables which are synchronous with the sensor clock too.
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access
Summary of Contents for SAM4S Series
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