Atmel SAM4S Series, Preliminary Data Sheet

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922
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
The status of the duty-cycle value write is reported in the “PWM Interrupt Status Register 2”
(PWM_ISR2) by the following flags:
• WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle
values and a new update period value. It is reset to 0 when the PWM_ISR2 register is read.
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by
these flags.
Sequence for Method 2:
1. Select the manual write of duty-cycle values and the automatic update by setting the
field UPDM to 1 in the PWM_SCM register
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
5. If an update of the period value and/or of the dead-time values is required, write regis-
ters that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to
Step 8.
6. Set UPDULOCK to 1 in PWM_SCUC.
7. The update of these registers will occur at the beginning of the next PWM period. At
this moment the bit UPDULOCK is reset, go to
Step 5. for new values.
8. If an update of the duty-cycle values and/or the update period is required, check first
that write of new update values is possible by polling the flag WRDY (or by waiting for
the corresponding interrupt) in the PWM_ISR2 register.
9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD).
10. The update of these registers will occur at the next PWM period of the synchronous
channels when the Update Period is elapsed. Go to Step 8. for new values.
Figure 37-11. Method 2 (UPDM=1)
CCNT0
CDTYUPD
0x20
0x40 0x60
UPRCNT 0x0 0x1
0x0
0x1 0x0
0x1
CDTY
0x20
0x40
UPRUPD 0x1
0x3
WRDY
0x60
0x0
0x1 0x2
0x3 0x0
0x1 0x2
UPR
0x1 0x3