Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 32-8. Master Write with One Byte Internal Address and Multiple Data Bytes
32.8.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
Figure 32-9 . When the
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
Figure 32-9 . When a multiple data byte read is
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 32-10 . For Internal Address usage see Section 32.8.6 .
Figure 32-9. Master Read with One Data Byte
A DATA n A S DADR W DATA n+1 A P DATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD IADR A
TWCK
A S DADR R DATA N P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD