Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the
array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds
the interrupt priority for interrupt n.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-
ters.
Table 11-29 shows how the interrupts, or IRQ numbers, map onto the interrupt registers
and corresponding CMSIS variables that have one bit per interrupt.
Note: 1. Each array element corresponds to a single NVIC register, for example the element ICER[0]
corresponds to the ICER0 register.
Table 11-29. Mapping of interrupts to the interrupt variables
Interrupts
CMSIS Array Elements
(1)
Set-enable Clear-enable Set-pending Clear-pending Active Bit
0-34 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0]
35-63 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1]