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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
the character lasts 1 bit time more, as the guard time length is the same and is added to the
error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character
in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Reg-
ister (US_SR) so that the software can handle the error.
Figure 34-31. T = 0 Protocol without Parity Error
Figure 34-32. T = 0 Protocol with Parity Error
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of
Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER
automatically clears the NB_ERRORS field.
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (US_MR). If INACK is to 1, no error signal is driven on the I/O
line even if a parity bit is detected.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding
Register, as if no error occurred and the RXRDY bit does rise.
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the
character before m oving on to the next one. Repetition is en abled by writin g the
MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character
can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as
the value loaded in MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the
Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the
receiver, the repetitions are stopped and the iteration counter is cleared.
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Parity
Bit
Baud Rate
Clock
Start
Bit
Guard
Time 1
Next
Start
Bit
Guard
Time 2
D0
D1
D2
D3
D4
D5
D6
D7
I/O
Parity
Bit
Baud Rate
Clock
Start
Bit
Guard
Time 1
Start
Bit
Guard
Time 2
D0
D1
Error
Repetition
Summary of Contents for SAM4S Series
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