Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
17.4.7.1 Wake Up Inputs
The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core
power supply. Each input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to
WKUPEN 15, in the Wake Up Inputs Register (SUPC_WUIR). The wake up level can be
selected with the corresponding polarity bit, WKUPPL0 to WKUPPL15, also located in
SUPC_WUIR.
All the resulting signals are wired-ORed to trigger a debounce counter, which can be pro-
grammed with the WKUPDBC field in the Supply Controller Wake Up Mode Register
(SUPC_WUMR). The WKUPDBC field can select a debouncing period of 3, 32, 512, 4,096 or
32,768 slow clock cycles. This corresponds respectively to about 100 µs, about 1 ms, about
16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Pro-
gramming WKUPDBC to 0x0 selects an immediate wake up, i.e., an enabled WKUP pin must be
active according to its polarity during a minimum of one slow clock period to wake up the core
power supply.
If an enabled WKUP pin is asserted for a time longer than the debouncing period, a wake up of
the core power supply is started and the signals, WKUP0 to WKUP15 as shown in
Figure 17-4 ,
are latched in the Supply Controller Status Register (SUPC_SR). This allows the user to identify
the source of the wake up, however, if a new wake up condition occurs, the primary information
is lost. No new wake up can be detected since the primary wake up condition has disappeared.
17.4.7.2 Low Power Debouncer Inputs
It is possible to generate a waveform (RTCOUT0 and RTCOUT1) in all modes (including backup
mode). It can be useful to control an external sensor and/or tampering function without waking
up the processor. Please refer to the RTC section.
Two separate debouncers are embedded for WKUP0 and WKUP1 inputs.
The WKUP0 and/or WKUP1 inputs can be programmed to perform a wake up of the core power
supply with a debouncing done by RTCOUT0. This can be enabled by setting LPDBC0 bit
and/or LPDBC1 bit in SUPC_WUMR.
In this mode of operation, WKUP0 and/or WKUP1 must not be configured to also act as
debouncing source for the WKUPDBC counter (WKUPEN0 and/or WKUPEN1 must be cleared
in SUPC_WUIR). Refer to
Figure 17-4 .
This mode of operation requires the RTC Output (RTCOUT0) to be configured to generate a
duty cycle programmable pulse (i.e. OUT0 = 0x7 in RTC_MR) in order to create the sampling
points of both debouncers. The sampling point is the falling edge of the RTCOUT0 waveform.
Figure 17-5 shows an example of an application where two tamper switches are used.
RTCOUTO0 powers the external pull-up used by the tampers.