Atmel SAM4S Series, Preliminary Data Sheet

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1073
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
41.4 Signal Description
41.5 Product Dependencies
41.5.1 Power Management
The DACC becomes active as soon as a conversion is requested and at least one channel is
enabled. The DACC is automatically deactivated when no channels are enabled.
For power saving options see Section 41.6.6 ”Sleep Mode” .
41.5.2 Interrupt Sources
The DACC interrupt line is connected on one of the internal sources of the interrupt controller.
Using the DACC interrupt requires the interrupt controller to be programmed first.
41.5.3 Conversion Performances
For performance and electrical characteristics of the DACC, see the product DC Characteristics
section.
41.6 Functional Description
41.6.1 Digital-to-Analog Conversion
The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is
named DACC Clock. Once a conversion starts the DACC takes 25 clock periods to provide the
analog result on the selected analog output.
41.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at the selected DACC
channel output and the EOC bit in the
DACC Interrupt Status Register , is set.
Reading the DACC_ISR register clears the EOC bit.
41.6.3 Conversion Triggers
In free running mode, conversion starts as soon as at least one channel is enabled and data is
written in the
DACC Conversion Data Register , then 25 DACC Clock periods later, the converted
data is available at the corresponding analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.
Warning: Disabling the external trigger mode automatically sets the DACC in free running
mode.
Table 41-1. DACC Pin Description
Pin Name Description
DAC0 - DAC1 Analog output channels
DATRG External triggers
Table 41-2. Peripheral IDs
Instance ID
DACC 30