Atmel SAM4S Series, Preliminary Data Sheet

Page: 1129 / 1163

1129
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
42.11.5.1 SSC Timings
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or
7(Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization. Figure
42-23 illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
3. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
4. 3.3V domain: V
VDDIO
from 2.85V to 3.6V, maximum external capacitor = 30 pF..
Table 42-43. SSC Timings
Symbol Parameter Condition Min Max Units
Transmitter
SSC
0
TK edge to TF/TD (TK output, TF output)
1.8v domain
(3)
3.3v domain
(4)
-3
-2.6
5.4
5.0
ns
SSC
1
TK edge to TF/TD (TK input, TF output)
1.8v domain
(3)
3.3v domain
(4)
4.5
3.8
16.3
13.3
ns
SSC
2
TF setup time before TK edge (TK output)
1.8v domain
(3)
3.3v domain
(4)
14.8
12.0
ns
SSC
3
TF hold time after TK edge (TK output)
1.8v domain
(3)
3.3v domain
(4)
0 ns
SSC
4
(1)
TK edge to TF/TD (TK output, TF input)
1.8v domain
(3)
3.3v domain
(4)
2.6(+2*t
CPMCK
)
(1)(4)
2.3(+2*t
CPMCK
)
(1)(4)
5.4(+2*t
CPMCK
)
(1)(4)
5.0(+2*t
CPMCK
)
(1)(4)
ns
SSC
5
TF setup time before TK edge (TK input)
1.8v domain
(3)
3.3v domain
(4)
0 ns
SSC
6
TF hold time after TK edge (TK input)
1.8v domain
(3)
3.3v domain
(4)
t
CPMCK
ns
SSC
7
(1)
TK edge to TF/TD (TK input, TF input)
1.8v domain
(3)
3.3v domain
(4)
4.5(+3*t
CPMCK
)
(1)(4)
3.8(+3*t
CPMCK
)
(1)(4)
16.3(+3*t
CPMCK
)
(1)(4)
13.3(+3*t
CPMCK
)
(1)(4)
ns
Receiver
SSC
8
RF/RD setup time before RK edge (RK input)
1.8v domain
(3)
3.3v domain
(4)
0 ns
SSC
9
RF/RD hold time after RK edge (RK input)
1.8v domain
(3)
3.3v domain
(4)
t
CPMCK
ns
SSC
10
RK edge to RF (RK input)
1.8v domain
(3)
3.3v domain
(4)
4.7
4
16.1
12.8
ns
SSC
11
RF/RD setup time before RK edge (RK output)
1.8v domain
(3)
3.3v domain
(4)
15.8 - t
CPMCK
12.5- t
CPMCK
ns
SSC
12
RF/RD hold time after RK edge (RK output)
1.8v domain
(3)
3.3v domain
(4)
t
CPMCK
- 4.3
t
CPMCK
- 3.6
ns
SSC
13
RK edge to RF (RK output)
1.8v domain
(3)
3.3v domain
(4)
-3
-2.6
4.3
3.8
ns