84
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
SMULBB, SMULBT
SMULTB, SMULTT
{Rd,} Rn, Rm
Signed Multiply (halfwords)
-
SMULL
RdLo, RdHi, Rn, Rm
Signed Multiply (32 x 32), 64-bit result
-
SMULWB, SMULWT
{Rd,} Rn, Rm
Signed Multiply word by halfword
-
SMUSD, SMUSDX
{Rd,} Rn, Rm
Signed dual Multiply Subtract
-
SSAT
Rd, #n, Rm {,shift #s}
Signed Saturate
Q
SSAT16
Rd, #n, Rm
Signed Saturate 16
Q
SSAX
{Rd,} Rn, Rm
Signed Subtract and Add with Exchange
GE
SSUB16
{Rd,} Rn, Rm
Signed Subtract 16
-
SSUB8
{Rd,} Rn, Rm
Signed Subtract 8
-
STM
Rn{!}, reglist
Store Multiple registers, increment after
-
STMDB, STMEA
Rn{!}, reglist
Store Multiple registers, decrement before
-
STMFD, STMIA
Rn{!}, reglist
Store Multiple registers, increment after
-
STR
Rt, [Rn, #offset]
Store Register word
-
STRB, STRBT
Rt, [Rn, #offset]
Store Register byte
-
STRD
Rt, Rt2, [Rn, #offset]
Store Register two words
-
STREX
Rd, Rt, [Rn, #offset]
Store Register Exclusive
-
STREXB
Rd, Rt, [Rn]
Store Register Exclusive byte
-
STREXH
Rd, Rt, [Rn]
Store Register Exclusive halfword
-
STRH, STRHT
Rt, [Rn, #offset]
Store Register halfword
-
STRT
Rt, [Rn, #offset]
Store Register word
-
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract
N,Z,C,V
SVC
#imm
Supervisor Call
-
SXTAB
{Rd,} Rn, Rm,{,ROR #}
Extend 8 bits to 32 and add
-
SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
-
SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
-
SXTB16
{Rd,} Rm {,ROR #n}
Signed Extend Byte 16
-
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
-
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
-
TBB
[Rn, Rm]
Table Branch Byte
-
TBH
[Rn, Rm, LSL #1]
Table Branch Halfword
-
TEQ
Rn, Op2
Test Equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UADD16
{Rd,} Rn, Rm
Unsigned Add 16
GE
UADD8
{Rd,} Rn, Rm
Unsigned Add 8
GE
USAX
{Rd,} Rn, Rm
Unsigned Subtract and Add with Exchange
GE
UHADD16
{Rd,} Rn, Rm
Unsigned Halving Add 16
-
UHADD8
{Rd,} Rn, Rm
Unsigned Halving Add 8
-
UHASX
{Rd,} Rn, Rm
Unsigned Halving Add and Subtract with Exchange
-
UHSAX
{Rd,} Rn, Rm
Unsigned Halving Subtract and Add with Exchange
-
Table 11-13. Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
Summary of Contents for SAM4S Series
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Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...