Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
24. Bus Matrix (MATRIX)
24.1 Description
The Bus Matrix (MATRIX) implements a multi-layer AHB that enables parallel access paths
between multiple AHB masters and slaves in a system, which increases the overall bandwidth.
Bus Matrix interconnects 4 AHB Masters to
5 AHB Slaves. The normal latency to connect a
master to a slave is one cycle except for the default master of the accessed slave which is con-
nected directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers
that allow to support application specific features.
24.2 Embedded Characteristics
24.2.1 Matrix Masters
The Bus Matrix manages 4 masters, which means that each master can perform an access con-
currently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
24.2.2 Matrix Slaves
The Bus Matrix manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration
per slave.
Table 24-1. List of Bus Matrix Masters
Master 0 Cortex-M4 Instruction/Data
Master 1 Cortex-M4 System
Master 2 Peripheral DMA Controller (PDC)
Master 3 CRC Calculation Unit
Table 24-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Internal Flash
Slave 3 External Bus Interface
Slave 4 Peripheral Bridge