Atmel SAM4S Series, Preliminary Data Sheet

Page: 933 / 1163

933
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
• Register group 2:
– “PWM Sync Channels Mode Register” on page 942
– “PWM Channel Mode Register” on page 970
– “PWM Stepper Motor Mode Register” on page 962
–
• Register group 3:
– “PWM Channel Period Register” on page 974
– “PWM Channel Period Update Register” on page 975
• Register group 4:
– “PWM Channel Dead Time Register” on page 977
– “PWM Channel Dead Time Update Register” on page 978
• Register group 5:
– “PWM Fault Mode Register” on page 956
– “PWM Fault Protection Value Register” on page 959
There are two types of Write Protect:
• Write Protect SW, which can be enabled or disabled.
• Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller
can disable it.
Both types of Write Protect can be applied independently to a particular register group by means
of the WPCMD and WPRG fields in PWM_WPCR register. If at least one Write Protect is active,
the register group is write-protected. The field WPCMD allows to perform the following actions
depending on its value:
• 0 = Disabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
• 1 = Enabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
• 2 = Enabling the Write Protect HW of the register groups of which the bit WPRG is at 1.
At any time, the user can determine which Write Protect is active in which register group by the
fields WPSWS and WPHWS in the
“PWM Write Protect Status Register” on page 965
(PWM_WPSR).
If a write access in a write-protected register is detected, then the WPVS flag in the
PWM_WPSR register is set and the field WPVSRC indicates in which register the write access
has been attempted, through its address offset without the two LSBs.
The WPVS and PWM_WPSR fields are automatically reset after reading the PWM_WPSR
register.