Atmel SAM4S Series, Preliminary Data Sheet

Page: 942 / 1163

942
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
37.7.9 PWM Sync Channels Mode Register
Name: PWM_SCM
Address: 0x40020020
Access: Read-write
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on
page 965 .
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in “PWM Sync Channels Update
Control Register” is set.
2. The update occurs when the Update Period is elapsed.
• PTRM: PDCDMA Transfer Request Mode
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
PTRCS PTRM – – UPDM
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – SYNC3 SYNC2 SYNC1 SYNC0
Value Name Description
0 MODE0 Manual write of double buffer registers and manual update of synchronous channels
(1)
1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels
(2)
2 MODE2
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous
channels
(2)
3 – Reserved
UPDM PTRM WRDY Flag and PDC Transfer Request
0 x
The WRDY flag in “PWM Interrupt Status Register 2” on page 949 and the PDC transfer request
are never set to 1.
1 x
The WRDY flag in “PWM Interrupt Status Register 2” on page 949 is set to 1 as soon as the
update period is elapsed, the PDC transfer request is never set to 1.
2
0
The WRDY flag in “PWM Interrupt Status Register 2” on page 949 and the PDC transfer request
are set to 1 as soon as the update period is elapsed.
1
The WRDY flag in “PWM Interrupt Status Register 2” on page 949 and the PDC transfer request
are set to 1 as soon as the selected comparison matches.