1152
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
SUPC
References to WFE instructions deleted in
Section 17.4.3 “Voltage Regulator Control/Backup Low Power
Supply monitor threshold values modified in
Section 17.4.4 “Supply Monitor” on page 307
.
SMTH bit table replaced by a cross-reference to Electrical characteristics in
Section 17.5.4 “Supply Controller
Supply Monitor Mode Register” on page 316
.
Section 17.5.8 “Supply Controller Status Register” on page 321
“half” replaced with “first half” in
Section 17.5.6 “Supply Controller Wake Up Mode Register” on page 318
and in
Section 17.4.7.2 “Low Power Debouncer Inputs” on page 311
.
modified.
added, title of
modified.
“square waveform ..” changed to “duty cycle ..” in
Section 17.4.7.2 “Low Power Debouncer Inputs” on page 311
Switching time of slow crystal oscillator updated in
Section 17.4.2 “Slow Clock Generator” on page 306
.
rfo
8024
8067
8064, 8082
8082
8226
8266
EEFC
Added GPNVM command line in
Section • “FARG: Flash Command Argument” on page 342
.
Unique identifier address changed in
Section 19.4.3.8 “Unique Identifier” on page 338
.
User Signature address changed in
Section 19.4.3.9 “User Signature” on page 338
Changed the System Controller base address from 0x400E0800 to 0x400E0A00 in
Embedded Flash Controller (EEFC) User Interface” on page 340
.
8076
8274
rfo
FFPI
All references, tables, figures related to 48-bit devices cleared in this whole chapter.
rfo
CMCC
New chapter.
CRCCU
Typos: CCIT802 corrected to CCITT802, CCIT16 corrected to CCITT16 in
Section 22.5.1 “CRC Calculation
and
Section 22.7.10 “CRCCU Mode Register” on page 387
Section 22.7.10 “CRCCU Mode Register” on page 387
7803
SMC
“turned out” changed to “switched to output mode” in
Section 25.8.4 “Write Mode” on page 426
.
Removed DBW which is not required for 8-bit only in
Section 25.15.4 “SMC MODE Register” on page 453
.
7925
8307
PMC
Added a note in
Section 27.2.16.7 “PMC Clock Generator Main Oscillator Register” on page 504
Max MULA/MULB value changed from 2047 to 62 in
Section 27.2.16.9 “PMC Clock Generator PLLA Register”
and
Section 27.2.16.10 “PMC Clock Generator PLLB Register” on page 508
Step 5 in
Section 27.2.13 “Programming Sequence” on page 489
: Master Clock option added in CSS field.
Third paragraph added in
Section 27.2.12 “Main Crystal Clock Failure Detector” on page 488
. WAITMODE bit
added in
Section 27.2.16.7 “PMC Clock Generator Main Oscillator Register” on page 504
.
7848
8064
8170
8208
CHIPID
modified.
rfo
TC
Changed TIOA1 in TIOB1 in
Section 35.6.14.1 “Description” on page 823
and
Section 35.6.14.4 “Position and
Rotation Measurement” on page 829
.
8101
Doc. Rev.
11100B
Comments
Change
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Summary of Contents for SAM4S Series
Page 44: ...44 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
Page 412: ...412 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
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Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...