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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
34.8.4
USART Mode Register (SPI_MODE)
Name:
US_MR (SPI_MODE)
Address:
0x40024004 (0), 0x40028004 (1)
Access:
Read-write
This configuration is relevant only if USART_MODE=0xE or 0xF in
“USART Mode Register” on page 774
This register can only be written if the WPEN bit is cleared in
“USART Write Protect Mode Register” on page 803
• USART_MODE: USART Mode of Operation
• USCLKS: Clock Selection
• CHRL: Character Length.
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
WRDBT
–
CPOL
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
CPHA
7
6
5
4
3
2
1
0
CHRL
USCLKS
USART_MODE
Value
Name
Description
0xE
SPI_MASTER
SPI Master
0xF
SPI_SLAVE
SPI Slave
Value
Name
Description
0
MCK
Master Clock MCK is selected
1
DIV
Internal Clock Divided MCK/DIV (DIV=8) is selected
3
SCK
Serial Clock SLK is selected
Value
Name
Description
3
8_BIT
Character length is 8 bits
Summary of Contents for SAM4S Series
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Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...