Atmel SAM4S Series, Preliminary Data Sheet

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162
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Examples
SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom
; halfword, sign extends to 32 bits, adds R8,and
; writes to R4
UXTAB R3, R4, R10 ; Extracts bottom byte of R10 and zero extends to
; 32 bits, adds R4, and writes to R3.
11.6.9 Bitfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in registers or
bitfields:
11.6.9.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
Operation
BFC
clears a bitfield in a register. It clears
width
bits in
Rd
, starting at the low bit position
lsb
. Other
bits in
Rd
are unchanged.
BFI
copies a bitfield into one register from another register. It replaces
width
bits in
Rd
starting at
the low bit position
lsb
, with
width
bits from
Rn
starting at bit[0]. Other bits in
Rd
are unchanged.
Restrictions
Do not use SP and do not use PC.
Table 11-24. Packing and Unpacking Instructions
Mnemonic Description
BFC Bit Field Clear
BFI Bit Field Insert
SBFX Signed Bit Field Extract
SXTB Sign extend a byte
SXTH Sign extend a halfword
UBFX Unsigned Bit Field Extract
UXTB Zero extend a byte
UXTH Zero extend a halfword
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield.
lsb
must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32- lsb .