Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
A predicted end of burst is used for defined length burst transfer, which is selected between the
following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will
never be broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat
boundary inside INCR transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat
boundary inside INCR transfer.
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat
boundary inside INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers
(MATRIX_MCFG).
24.5.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a
very slow slave (e.g. an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter
reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or
word transfer.
24.5.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master’s requests arise at the same
time, the master with the lowest number is first serviced then the others are serviced in a round-
robin manner.
There are three round-robin algorithm implemented:
• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master
24.5.2.1 Round-Robin arbitration without default master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access of a burst. Arbitration without
default master can be used for masters that perform significant bursts.
24.5.2.2 Round-Robin arbitration with last access master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. In fact, at the end of
the current transfer, if no other master request is pending, the slave remains connected to the
last master that performs the access. Other non privileged masters will still get one latency cycle
if they want to access the same slave. This technique can be used for masters that mainly per-
form single accesses.