Atmel SAM4S Series, Preliminary Data Sheet

Page: 45 / 1163

45
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
11. ARM Cortex-M4
11.1 Description
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcon-
troller market. It offers significant benefits to developers, including outstanding processing
performance combined with fast interrupt handling, enhanced system debug with extensive
breakpoint and trace capabilities, efficient processor core, system and memories, ultra-low
power consumption with integrated sleep modes, and platform security robustness
, with inte-
grated memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively opti-
mized design, providing high-end processing hardware including a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedi-
cated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4 processor implements a version of the
Thumb
®
instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4 instruction set provides the exceptional perfor-
mance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading
interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to
256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast
execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is
achieved through the hardware stacking of registers, and the ability to suspend load-multiple
and store-multiple operations. Interrupt handlers do not require wrapping in assembler code,
removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces
the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep
sleep function that enables the entire device to be rapidly powered down while still retaining pro-
gram state.
11.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA ® technology to provide high
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory
control, enabling applications to utilize multiple privilege levels, separating and protecting code,
data and stack on a task-by-task basis. Such requirements are becoming critical in many
embedded applications such as automotive.