Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 11-12. SRD Use
11.11.1.7 MPU Design Hints And Tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region
that the interrupt handlers might access.
Ensure the software uses aligned accesses of the correct size to access MPU registers:
• except for the MPU_RASR register, it must use aligned word accesses
• for the MPU_RASR register, it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused
regions to prevent any previous region settings from affecting the new MPU setup.
MPU Configuration for a Microcontroller
Usually, a microcontroller system has only a single processor and no caches. In such a system,
program the MPU as follows:
In most microcontroller implementations, the share ability and cache policy attributes do not
affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations. In special systems,
such as multiprocessor designs or designs with a separate DMA engine, the share ability attri-
bute might be important. In these cases, refer to the recommendations of the memory device
manufacturer.
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
Table 11-38. Memory region attributes for a microcontroller
Memory Region TEX C B S Memory Type and Attributes
Flash memory b000 1 0 0 Normal memory, non-shareable, write-through
Internal SRAM b000 1 0 1 Normal memory, shareable, write-through
External SRAM b000 1 1 1 Normal memory, shareable, write-back, write-allocate
Peripherals b000 0 1 1 Device memory, shareable