Atmel SAM4S Series Page 706 Preliminary Data Sheet Download

Page: 706 / 1163

706

11100B–ATARM–31-Jul-12

SAM4S Series [Preliminary]

32.11.8

TWI Interrupt Disable Register

Name: TWI_IDR

Address:

0x40018028 (0), 0x4001C028 (1)

Access:

Write-only

Reset:

0x00000000

• TXCOMP: Transmission Completed Interrupt Disable

• RXRDY: Receive Holding Register Ready Interrupt Disable

• TXRDY: Transmit Holding Register Ready Interrupt Disable

• SVACC: Slave Access Interrupt Disable

• GACC: General Call Access Interrupt Disable

• OVRE: Overrun Error Interrupt Disable

• NACK: Not Acknowledge Interrupt Disable

• ARBLST: Arbitration Lost Interrupt Disable

• SCL_WS: Clock Wait State Interrupt Disable

• EOSACC: End Of Slave Access Interrupt Disable

• ENDRX: End of Receive Buffer Interrupt Disable

• ENDTX: End of Transmit Buffer Interrupt Disable

• RXBUFF: Receive Buffer Full Interrupt Disable

• TXBUFE: Transmit Buffer Empty Interrupt Disable

0 = No effect.

1 = Disables the corresponding interrupt.

–

TXBUFE

RXBUFF

ENDTX

ENDRX

EOSACC

SCL_WS

ARBLST

NACK

–

OVRE

GACC

SVACC

–

TXRDY

RXRDY

TXCOMP

Summary of Contents for SAM4S Series

Page 1: ...d Backup modes down to 1 µA in Backup mode Ultra low power RTC Peripherals USB 2 0 Device 12 Mbps 2668 byte FIFO up to 8 bidirectional Endpoints On Chip Transceiver Up to 2 USARTs with ISO7816 IrDA RS 485 SPI Manchester and Modem Mode Two 2 wire UARTs Up to 2 Two Wire Interface I2C compatible 1 SPI 1 Serial Synchronous Controller I2S 1 High Speed Multimedia Card Interface SDIO SD Card MMC 2 Three ...

Page 2: ... Flash 2x USARTs 2x UARTs 2x TWIs 3x SPI an I2S as well as 1 PWM timer 2x three channel general purpose 16 bit timers with stepper motor and quadrature decoder logic support an RTC a 12 bit ADC a 12 bit DAC and an analog comparator The SAM4S series is ready for capacitive touch thanks to the QTouch library offering an easy way to implement buttons wheels and sliders The SAM4S device is a medium ra...

Page 3: ...kage LQFP 100 TFBGA 100 VFBGA 100 LQFP 64 QFN 64 LQFP 100 TFBGA 100 VFBGA 100 LQFP 64 QFN 64 LQFP 100 TFBGA 100 VFBGA 100 LQFP 64 QFN 64 LQFP 100 TFBGA 100 VFBGA 100 LQFP 64 QFN 64 LQFP 100 TFBGA 100 VFBGA 100 LQFP 64 QFN 64 Number of PIOs 79 47 79 47 79 47 79 47 79 47 External Bus Interface 8 bit data 4chip selects 24 bit address 8 bit data 4chip selects 24 bit address 8 bit data 4chip selects 24...

Page 4: ...TS1 CTS1 DSR1 DTR1 RI1 DCD1 NAND Flash Logic TWCK0 TWD0 TWD1 URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 TWCK1 ADVREF TIOB 0 2 TCLK 0 2 PWMH 0 3 PWML 0 3 PWMFI0 ADTRG TIOA 0 2 TST PCK0 PCK2 XIN NRST VDDCORE XOUT RTCOUT0 RTCOUT1 XIN32 XOUT32 ERASE VDDPLL VDDIO 12 bit DAC Temp Sensor PWM 12 bit ADC TWI0 TWI1 SPI SSC PIO Static Memory Controller Analog Comparator CRC Unit Peripheral Bridge 2668 ...

Page 5: ...0 SCK0 RTS0 CTS0 TWCK1 ADVREF TIOB 0 2 TCLK 0 2 PWMH 0 3 PWML 0 3 PWMFI0 ADTRG TIOA 0 2 TST PCK0 PCK2 XIN NRST VDDCORE XOUT RTCOUT0 RTCOUT1 XIN32 XOUT32 ERASE VDDPLL VDDIO 12 bit DAC Temp Sensor PWM 12 bit ADC TWI0 TWI1 SPI SSC PIO Analog Comparator CRC Unit Peripheral Bridge 2668 Bytes FIFO USB 2 0 Full Speed Transceiver NPCS0 PIODCCLK PIODCEN1 PIODCEN2 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK MCDA 0 3 M...

Page 6: ...0 3 PWMFI0 PDC UART0 UART1 URXD0 UTXD0 URXD1 UTXD1 SSC Peripheral Bridge PDC PIO PDC PDC 2668 Bytes FIFO USB 2 0 Full Speed VDDPLL VDDIO PDC RXD0 TXD0 USART0 SCK0 RTS0 CTS0 Analog Comparator CRC Unit ADC Transceiver PLLB In Circuit Emulator JTAG Serial Wire Flash Unique Identifier PMC PIOA PIOB PIOC ADTRG Cortex M4 Processor Fmax 120 MHz Timer Counter A Timer Counter B TWCK0 FLASH 2 1024 KBytes 2 ...

Page 7: ...CTS0 TWCK1 ADVREF TIOB 0 2 TCLK 0 2 PWMH 0 3 PWML 0 3 PWMFI0 ADTRG TIOA 0 2 TST PCK0 PCK2 XIN NRST VDDCORE XOUT RTCOUT0 RTCOUT1 XIN32 XOUT32 ERASE VDDPLL VDDIO 12 bit DAC Temp Sensor PWM 12 bit ADC TWI0 TWI1 SPI SSC PIO Analog Comparator CRC Unit Peripheral Bridge 2668 Bytes FIFO USB 2 0 Full Speed Transceiver NPCS0 PIODCCLK PIODCEN PIODCEN2 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK MCDA 0 3 MCCDA MCCK TF ...

Page 8: ... Input Input VDDIO Reset State PIO Input Internal Pull up disabled Schmitt Trigger enabled 1 XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output PCK0 PCK2 Programmable Clock Output Output Reset State PIO Input Internal Pull up enabled Schmitt Trigger enabled 1 Real Time Clock RTCOUT0 Programmable RTC waveform output Output VDDIO Res...

Page 9: ...el IO Controller B I O PC0 PC31 Parallel IO Controller C I O PIO Controller Parallel Capture Mode PIODC0 PIODC7 Parallel Capture Mode Data Input VDDIO PIODCCLK Parallel Capture Mode Clock Input PIODCEN1 2 Parallel Capture Mode Enable Input External Bus Interface D0 D7 Data Bus I O A0 A23 Address Bus Output NWAIT External Wait Signal Input Low Static Memory Controller SMC NCS0 NCS3 Chip Select Line...

Page 10: ... Transmit Frame Sync I O RF SSC Receive Frame Sync I O Timer Counter TC TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I O Line A I O TIOBx TC Channel x I O Line B I O Pulse Width Modulation Controller PWMC PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output only output in complementary mode when dead time insertion is enabled PW...

Page 11: ...O Analog ADVREF ADC DAC and Analog Comparator Reference Analog 12 bit Analog to Digital Converter ADC AD0 AD14 Analog Inputs Analog Digital ADTRG ADC Trigger Input VDDIO 12 bit Digital to Analog Converter DAC DAC0 DAC1 Analog output Analog Digital DACTRG DAC Trigger Input VDDIO Fast Flash Programming Interface FFPI PGMEN0 PGMEN2 Programming Enabling Input VDDIO PGMM0 PGMM3 Programming Mode Input V...

Page 12: ...age and Pinout 4 1 1 100 Lead LQFP Package Outline Figure 4 1 Orientation of the 100 lead LQFP Package 4 1 2 100 ball TFBGA Package Outline The 100 Ball TFBGA package has a 0 8 mm ball pitch and respects Green Standards Its dimensions are 9 x 9 x 1 1 mm Figure 4 2 shows the orientation of the 100 ball TFBGA Package Figure 4 2 Orientation of the 100 ball TFBGA Package 1 25 26 50 51 75 76 100 1 3 4 ...

Page 13: ...13 11100B ATARM 31 Jul 12 SAM4S Series Preliminary 4 1 3 100 ball VFBGA Package Outline Figure 4 3 Orientation of the 100 ball VFBGA Package ...

Page 14: ... PC21 10 VDDIN 35 PC5 60 NRST 85 VDDCORE 11 VDDOUT 36 VDDCORE 61 TST 86 PC22 12 PA17 PGMD5 AD0 37 PC4 62 PC9 87 ERASE PB12 13 PC26 38 PA25 PGMD13 63 PA29 88 DDM PB10 14 PA18 PGMD6 AD1 39 PA26 PGMD14 64 PA30 89 DDP PB11 15 PA21 PGMD9 AD8 40 PC3 65 PC10 90 PC23 16 VDDCORE 41 PA12 PGMD0 66 PA3 91 VDDIO 17 PC27 42 PA11 PGMM3 67 PA2 PGMEN2 92 PC24 18 PA19 PGMD7 AD2 43 PC2 68 PC11 93 PB13 DAC0 19 PC15 A...

Page 15: ...0 JTAGSEL D5 GND F10 PC9 J5 PA24 PGMD12 B1 PC30 D6 GND G1 PA21 PGMD9 AD8 J6 PA25 PGMD13 B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10 PGMM2 B3 GNDANA D8 PA2 PGMEN2 G3 PA15 PGMD3 J8 GND B4 PB14 DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO B6 PC20 E1 PA17 PGMD5 AD0 G6 PA26 PGMD14 K1 PA22 PGMD10 AD9 B7 PA31 E2 PC31 G7 PA12 PGMD0 K2 PC13 AD10 B8 PC19 E3 VDDIN G8 PC28 K3 PC12 AD12 B9...

Page 16: ... PGMD4 A9 PC19 D4 PC22 F9 TST J4 PC6 A10 TDO TRACESWO PB5 D5 PC5 F10 PC8 J5 PA24 B1 GNDANA D6 PA29 AD13 G1 PC15 AD11 J6 PA25 B2 PC25 D7 PA30 AD14 G2 PA19 PGMD7 AD2 J7 PA11 PGMM3 B3 PB14 DAC1 D8 GND G3 PA21 AD8 J8 VDDCORE B4 PB13 DAC0 D9 PC14 G4 PA15 PGMD3 J9 VDDCORE B5 PC23 D10 PC11 G5 PC3 J10 TDI PB4 B6 PC21 E1 VDDIN G6 PA10 PGMM2 K1 PA23 B7 TCK SWCLK PB7 E2 PB3 AD7 G7 PC1 K2 PC0 B8 PA31 E3 PB2 A...

Page 17: ...32 SD16 SA16 S16 S8 Package and Pinout 4 2 1 64 Lead LQFP Package Outline Figure 4 4 Orientation of the 64 lead LQFP Package 4 2 2 64 lead QFN Package Outline Figure 4 5 Orientation of the 64 lead QFN Package 33 49 48 32 17 16 1 64 1 16 17 32 33 48 49 64 TOP VIEW ...

Page 18: ...PA14 PGMD2 37 PA27 PGMD15 53 TCK SWCLK PB7 6 PB3 AD7 22 PA13 PGMD1 38 PA28 54 VDDCORE 7 VDDIN 23 PA24 PGMD12 39 NRST 55 ERASE PB12 8 VDDOUT 24 VDDCORE 40 TST 56 DDM PB10 9 PA17 PGMD5 AD0 25 PA25 PGMD13 41 PA29 57 DDP PB11 10 PA18 PGMD6 AD1 26 PA26 PGMD14 42 PA30 58 VDDIO 11 PA21 PGMD9 AD8 27 PA12 PGMD0 43 PA3 59 PB13 DAC0 12 VDDCORE 28 PA11 PGMM3 44 PA2 PGMEN2 60 GND 13 PA19 PGMD7 AD2 29 PA10 PGMM...

Page 19: ...he voltage regulator consumes less than 500 µA static current and draws 80 mA of output current Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current In Wait Mode quiescent current is only 5 µA In Backup mode the voltage regulator consumes less than 1µA while its output VDDOUT is driven internally to GND The default output voltage is 1 20V and the...

Page 20: ... when using a backup battery Since the PIO state is preserved when in backup mode any free PIO line can be used to switch off the external regulator by driving the PIO line at low level PIO is input pull up enabled after backup reset External wake up of the system can be from a push button or any signal See Section 5 6 Wake up Sources for further details Main Supply 1 62V 3 6V ADC DAC Analog Comp ...

Page 21: ...er are running The regulator and the core supply are off Backup mode is based on the Cortex M4 deep sleep mode with the voltage regulator disabled The SAM4S can be awakened from this mode through WUP0 15 pins the supply monitor SM the RTT or RTC wake up event Backup mode is entered by writing the Supply Controller Control Register SUPC_CR with the VROFF bit at 1 A key is needed to write the VROFF ...

Page 22: ...ernal events or internal events in order to wake up the core This is done by configuring the external lines WUP0 15 as fast startup wake up pins refer to Section 5 7 Fast Startup RTC or RTT Alarm and USB wake up events can be used to wake up the CPU Entering Wait Mode Select the 4 8 12 MHz fast RC oscillator as Main Clock Set the LPM bit in the PMC Fast Startup Mode Register PMC_FSMR Set the FLPM ...

Page 23: ... Total consumption 1 µA typ to 1 8V on VDDIO to 25 C 5 20 4 µA on VDDCORE 32 2 µA for total current consumption 6 Depends on MCK frequency 7 Depends on MCK frequency In this mode the core is supplied but some peripherals can be clocked Table 5 1 Low power Mode Configuration Summary Mode SUPC 32 kHz Osc RTC RTT Backup Registers POR Backup Region Regulator Core Memory Peripherals Mode Entry Potentia...

Page 24: ... which automatically reenables the core power supply and the SRAM power supply if they are not already enabled Figure 5 4 Wake up Source WKUP15 WKUPEN15 WKUPT15 WKUPEN1 WKUPEN0 Debouncer SLCK WKUPDBC WKUPS RTCEN rtc_alarm SMEN sm_out Core Supply Restart WKUPIS0 WKUPIS1 WKUPIS15 Falling Rising Edge Detector WKUPT0 Falling Rising Edge Detector WKUPT1 Falling Rising Edge Detector WKUP0 WKUP1 RTTEN rt...

Page 25: ... The fast restart circuitry as shown in Figure 5 5 is fully asynchronous and provides a fast start up signal to the Power Management Controller As soon as the fast start up signal is asserted the PMC automatically restarts the embedded 4 8 12 MHz Fast RC oscillator switches the mas ter clock on this 4 MHz clock and reenables the processor clock Figure 5 5 Fast Start Up Sources fast_restart WKUP15 ...

Page 26: ...p to 70 MHz for HSMCI MCK 2 70 MHz for SPI clock lines and 46 MHz on other lines See the AC Characteristics sub section of the product Electrical Characteristics Typical pull up and pull down value is 100 kΩ for all I Os Each I O line also embeds an ODT On Die Termination see Figure 6 1 below It consists of an internal series resistor termination scheme for impedance matching between the driver ou...

Page 27: ...guration of the pad for pull up triggers debouncing and glitch filters is possible regardless of the mode The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level It integrates a permanent pull down resistor of about 15 kΩ to GND so that it can be left uncon nected for normal operations By default the JTAG Debug Port is active If the debugger host wants to switch to t...

Page 28: ...et con troller can guarantee a minimum pulse length The NRST pin integrates a permanent pull up resistor to VDDIO of about 100 kΩ By default the NRST pin is configured as an input 6 5 ERASE Pin The ERASE pin is used to reinitialize the Flash content and some of its NVM bits to an erased state all bits read as logic level 1 It integrates a pull down resistor of about 100 kΩ to GND so that it can be...

Page 29: ... 0x40030000 UDP 33 0x40034000 ADC 29 0x40038000 DACC 30 0x4003C000 ACC 34 0x40040000 CRCCU 35 0x40044000 0x40048000 System Controller 0x400E0000 0x400E2600 0x40100000 0x40200000 0x40400000 0x60000000 External RAM SMC Chip Select 0 0x60000000 SMC Chip Select 1 Undefined 32 MBytes bit band alias 0x61000000 SMC Chip Select 2 0x62000000 SMC Chip Select 3 0x63000000 0x64000000 0x9FFFFFFF System Control...

Page 30: ... over System Cortex M4 bus at address 0x2000 0000 The SRAM is in the bit band region The bit band alias region is from 0x2200 0000 to 0x23FF FFFF 8 1 2 Internal ROM The SAM4S embeds an Internal ROM which contains the SAM Boot Assistant SAM BA In Application Programming routines IAP and Fast Flash Programming Interface FFPI At any time the ROM is mapped at address 0x0080 0000 8 1 3 Embedded Flash 8...

Page 31: ... The smaller sector 1 has 16 pages of 512 Bytes The larger sector has 96 pages of 512 Bytes From Sector 1 to n The rest of the array is composed of 64 KByte sectors of 128 pages each page of 512 bytes Refer to Figure 8 2 Flash Sector Organization below Small Sector 0 8 KBytes Small Sector 1 8 KBytes Larger Sector 48 KBytes Sector 1 64 KBytes 64 KBytes Sector n Sector 0 Sector size Sector name ...

Page 32: ... 2 x 512 KBytes Internal Flash0 address is 0x0040_0000 Internal Flash1 address is 0x0048_0000 SAM4SD32 the Flash size is 2 x 1024 KBytes Internal Flash0 address is 0x0040_0000 Internal Flash1 address is 0x0050_0000 Sector 0 Sector 1 Smaller sector 0 Smaller sector 1 Larger sector A sector size is 64 KBytes 16 pages of 512 Bytes 16 pages of 512 Bytes 96 pages of 512 Bytes 128 pages of 512 Bytes Sec...

Page 33: ...ng the Flash and writing the write buffer It also contains a User Inter face mapped on the APB The Enhanced Embedded Flash Controller ensures the interface of the Flash block It manages the programming erasing locking and unlocking sequences of the Flash using a full set of commands One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organiz...

Page 34: ...security bit can only be achieved by asserting the ERASE pin at 1 and after a full Flash erase is performed When the security bit is deactivated all accesses to the Flash SRAM Core registers Internal Peripherals are permitted It is important to note that the assertion of the ERASE pin should always be longer than 200 ms As the ERASE pin integrates a permanent pull down it can be left unconnected d...

Page 35: ...hrough the Clear GPNVM Bit and Set GPNVM Bit commands of the EEFC0 User Interface The GPNVM bits of the SAM4SA16 SD16 SD32 are only available on FLash0 There is no GPNVM bit on Flash1 The GPNVM0 is the security bit The GPNVM1 is used to select the boot mode boot always at 0x00 on ROM or FLASH The SAM4SD32 16 embeds an additional GPNVM bit GPNVM2 This GPNVM bit is used only to swap the Flash0 and F...

Page 36: ...old Time for Read Signals per Chip Select Programmable Setup Pulse And Hold Time for Write Signals per Chip Select Programmable Data Float Time per Chip Select External Wait Request Automatic Switch to Slow Clock Mode Asynchronous Read in Page Mode Supported Page Size Ranges from 4 to 32 Bytes NAND Flash additional logic supporting NAND Flash with Multiplexed Data Address buses Hardware Configurab...

Page 37: ...et proc_nreset periph_nreset ice_nreset Master Clock MCK SLCK NRST MAINCK FSTT0 FSTT15 XIN32 XOUT32 osc32k_xtal_en Slow Clock SLCK osc32k_rc_en VDDIO VDDCORE VDDOUT ADVREF ADx WKUP0 WKUP15 bod_core_on lcore_brown_out RTT rtt_alarm SLCK rtt_nreset XIN XOUT VDDIO VDDIN PIOx USB Transeivers VDDIO DDP DDM MAINCK DAC Analog Circuitry DACx PLLB PLLBCK PLLACK Embedded 12 8 4 MHz RC Oscillator Main Clock ...

Page 38: ... 9 2 2 Brownout Detector on VDDCORE The Brownout Detector monitors VDDCORE It is active by default It can be deactivated by soft ware through the Supply Controller SUPC_MR It is especially recommended to disable it during low power modes such as wait or sleep modes If VDDCORE goes below the threshold voltage the reset of the core is asserted For more infor mation refer to the Supply Controller SUP...

Page 39: ...ower Management Controller 6 EEFC0 X Enhanced Embedded Flash Controller 0 7 EEFC1 Enhanced Embedded Flash Controller 1 8 UART0 X X UART 0 9 UART1 X X UART 1 10 SMC X X Static Memory Controller 11 PIOA X X Parallel I O Controller A 12 PIOB X X Parallel I O Controller B 13 PIOC X X Parallel I O Controller C 14 USART0 X X USART 0 15 USART1 X X USART 1 16 Reserved 17 Reserved 18 HSMCI X X Multimedia C...

Page 40: ... multiplexing tables in the following paragraphs define how the I O lines of the peripherals A B and C are multiplexed on the PIO Controllers The column Comments has been inserted in this table for the user s own com ments it may be used to track how pins are defined in an application Note that some peripheral functions which are output only might be duplicated within the tables 31 PWM X X Pulse W...

Page 41: ...14 SPCK PWMH3 WKUP8 PA15 TF TIOA1 PWML3 WKUP14 PIODCEN1 PA16 TK TIOB1 PWML2 WKUP15 PIODCEN2 PA17 TD PCK1 PWMH3 AD0 PA18 RD PCK2 A14 AD1 PA19 RK PWML0 A15 AD2 WKUP9 PA20 RF PWML1 A16 AD3 WKUP10 PA21 RXD1 PCK1 AD8 64 100 pins versions PA22 TXD1 NPCS3 NCS2 AD9 64 100 pins versions PA23 SCK1 PWMH0 A19 PIODCCLK 64 100 pins versions PA24 RTS1 PWMH1 A20 PIODC0 64 100 pins versions PA25 CTS1 PWMH2 A23 PIO...

Page 42: ...ral B Peripheral C Extra Function System Function Comments PB0 PWMH0 AD4 RTCOUT0 PB1 PWMH1 AD5 RTCOUT1 PB2 URXD1 NPCS2 AD6 WKUP12 PB3 UTXD1 PCK2 AD7 PB4 TWD1 PWMH2 TDI PB5 TWCK1 PWML0 WKUP13 TDO TRACESWO PB6 TMS SWDIO PB7 TCK SWCLK PB8 XOUT PB9 XIN PB10 DDM PB11 DDP PB12 PWML1 ERASE PB13 PWML2 PCK0 DAC0 64 100 pins versions PB14 NPCS1 PWMH3 DAC1 64 100 pins versions ...

Page 43: ...ion PC10 NANDWE 100 pin version PC11 NRD 100 pin version PC12 NCS3 AD12 100 pin version PC13 NWAIT PWML0 AD10 100 pin version PC14 NCS0 100 pin version PC15 NCS1 PWML1 AD11 100 pin version PC16 A21 NANDALE 100 pin version PC17 A22 NANDCLE 100 pin version PC18 A0 PWMH0 100 pin version PC19 A1 PWMH1 100 pin version PC20 A2 PWMH2 100 pin version PC21 A3 PWMH3 100 pin version PC22 A4 PWML3 100 pin ver...

Page 44: ...44 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...

Page 45: ...des the exceptional perfor mance expected of a modern 32 bit architecture with the high code density of 8 bit and 16 bit microcontrollers The Cortex M4 processor closely integrates a configurable NVIC to deliver industry leading interrupt performance The NVIC includes a non maskable interrupt NMI and provides up to 256 interrupt priority levels The tight integration of the processor core and NVIC ...

Page 46: ...mable memory for example flash is available in the device During initialization the application in ROM detects from the programmable memory whether a patch is required If a patch is required the applica tion programs the FPB to remap a number of addresses When those addresses are accessed the accesses are redirected to a remap table specified in the FPB configuration which means the program in the...

Page 47: ...y 11 3 Block Diagram Figure 11 1 Typical Cortex M4 Implementation NVIC Debug Access Port Memory Protection Unit Serial Wire Viewer Bus Matrix Code Interface SRAM and Peripheral Interface Data Watchpoints Flash Patch Cortex M4 Processor Processor Core ...

Page 48: ...l Privileged The software can use all the instructions and has access to all resources Privileged software executes at the privileged level In Thread mode the CONTROL register controls whether the software execution is privileged or unprivileged see CONTROL Register In Handler mode software execution is always privileged Only privileged software can write to the CONTROL register to change the priv...

Page 49: ...tack 1 Handler Exception handlers Always privileged Main stack SP R13 LR R14 PC R15 R5 R6 R7 R0 R1 R3 R4 R2 R10 R11 R12 R8 R9 Low registers High registers MSP PSP PSR PRIMASK FAULTMASK BASEPRI CONTROL General purpose registers Stack Pointer Link Register Program Counter Program status register Exception mask registers CONTROL register Special registers Banked version of SP Table 11 2 Core Processo...

Page 50: ...the LR value 0xFFFFFFFF 11 4 1 7 Program Counter The Program Counter PC is register R15 It contains the current program address On reset the processor loads the PC with the value of the reset vector which is at address 0x00000004 Bit 0 of the value is loaded into the EPSR T bit at reset and must be 1 Link Register LR Read write Either 0xFFFFFFFF Program Counter PC Read write Either See description...

Page 51: ...e read all of the registers using PSR with the MRS instruction write to the APSR N Z C V and Q bits using APSR_nzcvq with the MSR instruction The PSR combinations and attributes are Notes 1 he processor ignores writes to the IPSR bits 2 Reads of the EPSR bits return zero and the processor ignores writes to the these bits See the instruction descriptions MRS and MSR for more information about how t...

Page 52: ...in a carry bit or subtract operation resulted in a borrow bit 1 add operation resulted in a carry bit or subtract operation did not result in a borrow bit V Overflow Flag 0 operation did not result in an overflow 1 operation resulted in an overflow Q DSP Overflow and Saturation Flag Sticky saturation flag 0 indicates that saturation has not occurred since reset or since the bit was last cleared to...

Page 53: ...upt Service Routine ISR ISR_NUMBER Number of the Current Exception 0 Thread mode 1 Reserved 2 NMI 3 Hard fault 4 Memory management fault 5 Bus fault 6 Usage fault 7 10 Reserved 11 SVCall 12 Reserved for Debug 13 Reserved 14 PendSV 15 SysTick 16 IRQ0 50 IRQ34 See Exception Types for more information 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ISR_NUMBER 7 6 5 4 3 2 1 0 ISR...

Page 54: ...ly stores the next register operand in the multiple operation to EPSR bits 15 12 After servicing the interrupt the processor returns to the register pointed to by bits 15 12 resumes the execution of the multiple load or store instruction When the EPSR holds the ICI execution state bits 26 25 11 10 are zero IT If Then Instruction Indicates the execution state bits of the IT instruction The If Then ...

Page 55: ...nd MRS instructions or the CPS instruc tion to change the value of PRIMASK or FAULTMASK See MRS MSR and CPS for more information 11 4 1 13 Priority Mask Register Name PRIMASK Access Read write Reset 0x000000000 The PRIMASK register prevents the activation of all exceptions with a configurable priority PRIMASK 0 no effect 1 prevents the activation of all exceptions with a configurable priority 31 3...

Page 56: ...revents the activation of all exceptions except for Non Maskable Interrupt NMI FAULTMASK 0 No effect 1 Prevents the activation of all exceptions except for NMI The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FAULTMASK ...

Page 57: ...x0000 no effect Nonzero defines the base priority for exception processing The processor does not process any exception with a priority value greater than or equal to BASEPRI This field is similar to the priority fields in the interrupt priority registers The processor implements only bits 7 4 of this field bits 3 0 read as zero and ignore writes See Interrupt Priority Registers for more informati...

Page 58: ...tack pointer bit of the CON TROL register when in Handler mode The exception entry and return mechanisms update the CONTROL register based on the EXC_RETURN value In an OS environment ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack By default the Thread mode uses the MSP To switch the stack pointer used in Thread mod...

Page 59: ...controller Software Interface Standard CMSIS defines a common way to access peripheral registers define exception vectors the names of the registers of the core peripherals the core exception vectors a device independent interface for RTOS kernels including a debug channel The CMSIS includes address definitions and data structures for the core peripherals in the Cor tex M4 processor The CMSIS simp...

Page 60: ... this product refer to the Memories section of the datasheet 11 4 2 1 Memory Regions Types and Attributes The memory map and the programming of the MPU split the memory map into regions Each region has a defined memory type and some regions have additional memory attributes The memory type and attributes determine the behavior of accesses to the region Vendor specific memory External device Extern...

Page 61: ...the processor prevents instruction accesses A fault exception is generated only on execution of an instruction executed from an XN region 11 4 2 2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions providing t...

Page 62: ...ditional access con straints and some regions are subdivided as Table 11 5 shows Table 11 4 Memory Access Behavior Address Range Memory Region Memory Type XN Description 0x00000000 0x1FFFFFFF Code Normal 1 Executable region for program code Data can also be put here 0x20000000 0x3FFFFFFF SRAM Normal 1 Executable region for data Code can also be put here This region includes bit band and bit band a...

Page 63: ...here the memory sys tem guarantees the order of memory accesses Otherwise if the order of memory accesses is critical the software must include memory barrier instructions to force that ordering The proces sor provides the following memory barrier instructions DMB The Data Memory Barrier DMB instruction ensures that outstanding memory transactions com plete before subsequent memory transactions Se...

Page 64: ...the bit band region bit_word_offset byte_offset x 32 bit_number x 4 bit_word_addr bit_band_base bit_word_offset where Bit_word_offset is the position of the target bit in the bit band memory region Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit Table 11 6 SRAM Memory Bit banding Regions Address Range Memory Region Instruction and Data Accesses 0x2...

Page 65: ...ias region updates a single bit in the bit band region Bit 0 of the value written to a word in the alias region determines the value written to the tar geted bit in the bit band region Writing a value with bit 0 set to 1 writes a 1 to the bit band bit and writing a value with bit 0 set to 0 writes a 0 to the bit band bit Bits 31 1 of the alias word have no effect on the bit band bit Writing 0x01 h...

Page 66: ... to obtain exclusive access to a memory location The software can use them to perform a guaranteed read modify write memory update sequence or for a semaphore mechanism A pair of synchronization primitives comprises A Load exclusive Instruction used to read the value of a memory location requesting exclu sive access to that location A Store Exclusive instruction used to attempt to write to the sam...

Page 67: ...e Cortex M4 includes an exclusive access monitor that tags the fact that the processor has executed a Load Exclusive instruction If the processor is part of a multiprocessor system the system also globally tags the memory locations addressed by exclusive accesses by each processor The processor removes its exclusive access tag if It executes a CLREX instruction It executes a Store Exclusive instru...

Page 68: ...r example the following C code generates the require LDREXB operation __ldrex volatile char 0xFF STREX uint32_t __STREXW uint32_t value uint32_t addr STREXH uint32_t __STREXH uint16_t value uint16_t addr STREXB uint32_t __STREXB uint8_t value uint8_t addr CLREX void __CLREX void Table 11 8 CMSIS Functions for Exclusive Access Instructions Continued Instruction CMSIS Function ...

Page 69: ...eset is invoked on power up or a warm reset The exception model treats reset as a special form of exception When reset is asserted the operation of the processor stops potentially at any point in an instruction When reset is deasserted execution restarts from the address pro vided by the reset entry in the vector table Execution restarts as privileged execution in Thread mode Non Maskable Interrup...

Page 70: ...em an unaligned address on word and halfword memory access a division by zero SVCall A supervisor call SVC is an exception that is triggered by the SVC instruction In an OS envi ronment applications can use SVC instructions to access OS kernel functions and device drivers PendSV PendSV is an interrupt driven request for system level service In an OS environment use PendSV for context switching whe...

Page 71: ...e Fault Handling 11 4 3 3 Exception Handlers The processor handles exceptions using Interrupt Service Routines ISRs Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs Fault Handlers Hard fault memory management fault usage fault bus fault are fault exceptions handled by the fault handlers System Handlers NMI PendSV SVCall SysTick and the fault exceptions are all system exceptions that are...

Page 72: ...t Register 11 4 3 5 Exception Priorities As Table 11 9 shows all exceptions have an associated priority with a lower priority value indicating a higher priority configurable priorities for all exceptions except Reset Hard fault and NMI If the software does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For information about configuring exception ...

Page 73: ...group Only the group priority determines preemption of interrupt exceptions When the processor is executing an interrupt exception handler another interrupt with the same group priority as the interrupt being handled does not preempt the handler If multiple pending interrupts have the same group priority the subpriority field determines the order in which they are processed If multiple pending int...

Page 74: ...iginal exception enters the execute stage of the processor On return from the exception handler of the late arriving exception the normal tail chaining rules apply Exception Entry An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of a higher priority than the exception being handled in which case ...

Page 75: ...cessor writes an EXC_RETURN value to the LR This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred If no higher priority exception occurs during the exception entry the processor starts executing the exception handler and automatically changes the status of the corresponding pending inter rupt to active If another hi...

Page 76: ...generate a fault a bus error on an instruction fetch or vector table load a data access an internally detected error such as an undefined instruction an attempt to execute an instruction from a memory region marked as Non Executable XN a privilege violation or an attempt to access an unmanaged region causing an MPU fault Fault Types Table 11 11 shows the types of fault the handler used for the fau...

Page 77: ... because a fault handler cannot preempt itself it must have the same priority as the current priority level A fault handler causes a fault with the same or lower priority as the fault it is servicing This is because the handler for the new fault cannot preempt the currently executing fault handler An exception handler causes a fault for which the priority is the same as or lower than the currently...

Page 78: ...egister indicates the address accessed by the operation that caused the fault as shown in Table 11 12 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers When the processor is in lockup state it does not execute any instructions The pro cessor remains in lockup state until either it is reset an NMI occurs it is halted by a debugger Note I...

Page 79: ...it event register When the processor executes a WFE instruction it checks this register if the register is 0 the processor stops executing instructions and enters sleep mode if the register is 1 the processor clears the register to 0 and continues executing instructions without entering sleep mode See WFE for more information 11 5 1 3 Sleep On Exit If the SLEEPONEXIT bit of the SCR is set to 1 whe...

Page 80: ...d or has insufficient priority to cause an exception entry For more information about the SCR see System Control Register 11 5 2 3 External Event Input The processor provides an external event input signal Peripherals can drive this signal either to wake the processor from WFE or to set the internal WFE event register to 1 to indicate that the processor must not enter sleep mode on a later WFE ins...

Page 81: ...Add with Carry N Z C V ADD ADDS Rd Rn Op2 Add N Z C V ADD ADDW Rd Rn imm12 Add N Z C V ADR Rd label Load PC relative address AND ANDS Rd Rn Op2 Logical AND N Z C ASR ASRS Rd Rm Rs n Arithmetic Shift Right N Z C B label Branch BFC Rd lsb width Bit Field Clear BFI Rd Rn lsb width Bit Field Insert BIC BICS Rd Rn Op2 Bit Clear N Z C BKPT imm Breakpoint BL label Branch with Link BLX Rm Branch indirect ...

Page 82: ... n Logical Shift Left N Z C LSR LSRS Rd Rm Rs n Logical Shift Right N Z C MLA Rd Rn Rm Ra Multiply with Accumulate 32 bit result MLS Rd Rn Rm Ra Multiply and Subtract 32 bit result MOV MOVS Rd Op2 Move N Z C MOVT Rd imm16 Move Top MOVW MOV Rd imm16 Move 16 bit constant N Z C MRS Rd spec_reg Move from special register to general register MSR spec_reg Rm Move from general register to special registe...

Page 83: ... Signed Halving Add 8 SHASX Rd Rn Rm Signed Halving Add and Subtract with Exchange SHSAX Rd Rn Rm Signed Halving Subtract and Add with Exchange SHSUB16 Rd Rn Rm Signed Halving Subtract 16 SHSUB8 Rd Rn Rm Signed Halving Subtract 8 SMLABB SMLABT SMLATB SMLATT Rd Rn Rm Ra Signed Multiply Accumulate Long halfwords Q SMLAD SMLADX Rd Rn Rm Ra Signed Multiply Accumulate Dual Q SMLAL RdLo RdHi Rn Rm Signe...

Page 84: ...re Register Exclusive byte STREXH Rd Rt Rn Store Register Exclusive halfword STRH STRHT Rt Rn offset Store Register halfword STRT Rt Rn offset Store Register word SUB SUBS Rd Rn Op2 Subtract N Z C V SUB SUBW Rd Rn imm12 Subtract N Z C V SVC imm Supervisor Call SXTAB Rd Rn Rm ROR Extend 8 bits to 32 and add SXTAB16 Rd Rn Rm ROR Dual extend 8 bits to 16 and add SXTAH Rd Rn Rm ROR Extend 16 bits to 3...

Page 85: ...gned Saturating Add 16 UQADD8 Rd Rn Rm Unsigned Saturating Add 8 UQASX Rd Rn Rm Unsigned Saturating Add and Subtract with Exchange UQSAX Rd Rn Rm Unsigned Saturating Subtract and Add with Exchange UQSUB16 Rd Rn Rm Unsigned Saturating Subtract 16 UQSUB8 Rd Rn Rm Unsigned Saturating Subtract 8 USAD8 Rd Rn Rm Unsigned Sum of Absolute Differences USADA8 Rd Rn Rm Ra Unsigned Sum of Absolute Differences...

Page 86: ... uint32_t int value REV16 uint32_t __REV16 uint32_t int value REVSH uint32_t __REVSH uint32_t int value RBIT uint32_t __RBIT uint32_t int value SEV void __SEV void WFE void __WFE void WFI void __WFI void Table 11 15 CMSIS Intrinsic Functions to Access the Special Registers Special Register Access CMSIS Function PRIMASK Read uint32_t __get_PRIMASK void Write void __set_PRIMASK uint32_t value FAULTM...

Page 87: ... second operand This is shown as Operand2 in the descriptions of the syntax of each instruction Operand2 can be a Constant Register with Optional Shift Constant Specify an Operand2 constant in the form constant where constant can be any constant that can be produced by shifting an 8 bit value left by any number of bits within a 32 bit word any constant of the form 0x00XY00XY any constant of the fo...

Page 88: ...t is written to a destination register During the calculation of Operand2 by the instructions that specify the second operand as a register with shift See Flexible Second Operand The result is used by the instruction The permitted shift lengths depend on the shift type and the instruction If the shift length is 0 no shift occurs Register shift operations update the carry flag except when the speci...

Page 89: ...t is updated to 0 Figure 11 8 LSR 3 LSL Logical shift left by n bits moves the right hand 32 n bits of the register Rm to the left by n places into the left hand 32 n bits of the result And it sets the right hand n bits of the result to 0 See Figure 11 9 The LSL n operation can be used to multiply the value in the register Rm by 2n if the value is regarded as an unsigned integer or a two s complem...

Page 90: ...tation bit n 1 of the register Rm If n is 32 then the value of the result is same as the value in Rm and if the carry flag is updated it is updated to bit 31 of Rm ROR with shift length n more than 32 is the same as ROR with shift length n 32 Figure 11 10 ROR 3 RRX Rotate right with extend moves the bits of the register Rm to the right by one bit And it copies the carry flag into bit 31 of the res...

Page 91: ...rrent instruc tion If the offset is too big the assembler produces an error For B BL CBNZ and CBZ instructions the value of the PC is the address of the current instruction plus 4 bytes For all other instructions that use labels the value of the PC is the address of the current instruction plus 4 bytes with bit 1 of the result cleared to 0 to make it word aligned Your assembler might permit other ...

Page 92: ...ry occurs if the result of an addition is greater than or equal to 232 if the result of a subtraction is positive or zero as the result of an inline barrel shifter operation in a move or logical instruction An overflow occurs when the sign of the result in bit 31 does not match the sign of the result had the operation been performed at infinite precision for example if adding two negative values r...

Page 93: ...and R1 setting flags ITT GT IT instruction for the two GT conditions CMPGT R2 R3 If greater than compare R2 and R3 setting flags MOVGT R4 R5 If still greater than do R4 R5 11 6 3 8 Instruction Width Selection There are many instructions that can generate either a 16 bit encoding or a 32 bit encoding depending on the operands and destination register specified For some of these instructions Table 1...

Page 94: ...low shows instructions with the instruction width suffix BCS W label creates a 32 bit instruction even for a short branch ADDS W R0 R0 R1 creates a 32 bit instruction even though the same operation can be done by a 16 bit instruction 11 6 4 Memory Access Instructions The table below shows the memory access instructions Table 11 17 Memory Access Instructions Mnemonic Description ADR Load PC relativ...

Page 95: ... code because the address is PC relative If ADR is used to generate a target address for a BX or BLX instruction ensure that bit 0 of the address generated is set to 1 for correct execution Values of label must be within the range of 4095 to 4095 from the address in the PC Note The user might have to use the W suffix to get the maximum offset range or to generate addresses that are not word aligne...

Page 96: ... 32 bits on loads SH signed halfword sign extend to 32 bits LDR only omit for word cond is an optional condition code see Conditional Execution Rt is the register to load or store Rn is the register on which the memory address is based offset is an offset from Rn If offset is omitted the address is the contents of Rn Rt2 is the additional register to load or store for two word operations Operation...

Page 97: ...diate pre indexed and post indexed forms Restrictions For load instructions Rt can be SP or PC for word loads only Rt must be different from Rt2 for two word loads Rn must be different from Rt and Rt2 in the pre indexed or post indexed forms When Rt is PC in a word load instruction Bit 0 of the loaded value must be 1 for correct execution A branch occurs to the address created by changing bit 0 of...

Page 98: ...ord 4 bytes above the address in R8 and then decrement R8 by 16 11 6 4 3 LDR and STR Register Offset Load and Store with register offset Syntax op type cond Rt Rn Rm LSL n where op is one of LDR Load Register STR Store Register type is one of B unsigned byte zero extend to 32 bits on loads SB signed byte sign extend to 32 bits LDR only H unsigned halfword zero extend to 32 bits on loads SH signed ...

Page 99: ...is halfword aligned address If the instruction is conditional it must be the last instruction in the IT block Condition Flags These instructions do not change the flags Examples STR R0 R5 R1 Store value of R0 into an address equal to sum of R5 and R1 LDRSB R0 R5 R1 LSL 1 Read byte value from an address equal to sum of R5 and two times R1 sign extended it to a word value and put it in R0 STR R0 R1 ...

Page 100: ...me way as nor mal memory access instructions with immediate offset Restrictions In these instructions Rn must not be PC Rt must not be SP and must not be PC Condition Flags These instructions do not change the flags Examples STRBTEQ R4 R7 Conditionally store least significant byte in R4 to an address in R7 with unprivileged access LDRHT R2 R2 8 Load halfword value from an address equal to sum of R...

Page 101: ...e maximum offset range See Instruction Width Selection Restrictions In these instructions Rt can be SP or PC only for word loads Rt2 must not be SP and must not be PC Rt must be different from Rt2 When Rt is PC in a word load instruction bit 0 of the loaded value must be 1 for correct execution and a branch occurs to this halfword aligned address if the instruction is conditional it must be the la...

Page 102: ... a synonym for LDMDB and refers to its use for popping data from Empty Ascending stacks STM and STMEA are synonyms for STMIA STMEA refers to its use for pushing data onto Empty Ascending stacks STMFD is s synonym for STMDB and refers to its use for pushing data onto Full Descending stacks Operation LDM instructions load the registers in reglist with word values from memory addresses based on Rn ST...

Page 103: ...P in any STM instruction reglist must not contain PC in any LDM instruction reglist must not contain PC if it contains LR reglist must not contain Rn if the writeback suffix is specified When PC is in reglist in an LDM instruction bit 0 of the value loaded to the PC must be 1 for correct execution and a branch occurs to this halfword aligned address if the instruction is conditional it must be the...

Page 104: ...ter numbers with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address POP loads registers from the stack in order of increasing register numbers with the lowest num bered register using the lowest memory address and the highest numbered register using the highest memory address See LDM and STM for more information Restricti...

Page 105: ...n must also have the same data size as the value loaded by the preceding Load exclusive instruction This means software must always use a Load exclusive instruction and a matching Store Exclusive instruction to perform a synchronization operation see Syn chronization Primitives If an Store Exclusive instruction performs the store it writes 0 to its destination register If it does not perform the s...

Page 106: ... 4 9 CLREX Clear Exclusive Syntax CLREX cond where cond is an optional condition code see Conditional Execution Operation Use CLREX to make the next STREX STREXB or STREXH instruction write 1 to its destination register and fail to perform the store It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and th...

Page 107: ... MOV Move MOVT Move Top MOVW Move 16 bit constant MVN Move NOT ORN Logical OR NOT ORR Logical OR RBIT Reverse Bits REV Reverse byte order in a word REV16 Reverse byte order in each halfword REVSH Reverse byte order in bottom halfword and sign extend ROR Rotate Right RRX Rotate Right with Extend RSB Reverse Subtract SADD16 Signed Add 16 SADD8 Signed Add 8 SASX Signed Add and Subtract with Exchange ...

Page 108: ...e USAX Unsigned Subtract and Add with Exchange UHADD16 Unsigned Halving Add 16 UHADD8 Unsigned Halving Add 8 UHASX Unsigned Halving Add and Subtract with Exchange UHSAX Unsigned Halving Subtract and Add with Exchange UHSUB16 Unsigned Halving Subtract 16 UHSUB8 Unsigned Halving Subtract 8 USAD8 Unsigned Sum of Absolute Differences USADA8 Unsigned Sum of Absolute Differences and Accumulate USUB16 Un...

Page 109: ...to the ADD syntax that uses the imm12 operand SUBW is equivalent to the SUB syntax that uses the imm12 operand Restrictions In these instructions Operand2 must not be SP and must not be PC Rd can be SP only in ADD and SUB and only with the additional restrictions Rn must also be SP any shift in Operand2 must be limited to a maximum of 3 bits using LSL Rn can be SP only in ADD and SUB Rd can be PC ...

Page 110: ... is ignored a branch occurs to the address created by forcing bit 0 of that value to 0 Condition Flags If S is specified these instructions update the N Z C and V flags according to the result Examples ADD R2 R1 R3 SUBS R8 R6 240 Sets the flags on the result RSB R4 R4 1280 Subtracts contents of R4 from 1280 ADCHI R11 R0 R3 Only executed if C flag set and Z flag clear Multiword arithmetic examples ...

Page 111: ... If S is specified these instructions update the N and Z flags according to the result can update the C flag during the calculation of Operand2 see Flexible Second Operand do not affect the V flag Examples AND R9 R2 0xFF00 ORREQ R2 R0 R5 ANDS R9 R8 0x19 EORS R7 R11 0x18181818 BIC R0 R1 0xab ORN R7 R11 R14 ROR 4 ORNS R7 R11 R14 ASR 32 op is one of AND logical AND ORR logical OR or bit set EOR logic...

Page 112: ...ctions Do not use SP and do not use PC Condition Flags If S is specified these instructions update the N and Z flags according to the result the C flag is updated to the last bit shifted out except when the shift length is 0 see Shift Operations op is one of ASR Arithmetic Shift Right LSL Logical Shift Left LSR Logical Shift Right ROR Rotate Right S is an optional suffix If S is specified the cond...

Page 113: ...xtend 11 6 5 4 CLZ Count Leading Zeros Syntax CLZ cond Rd Rm where Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd The result value is 32 if no bits are set and zero if bit 31 is set Restrictions Do not use SP and do not use PC Condition Flags This instruction does not change the flags Examples CLZ R4 R9 CLZNE R2 R3 cond is an option...

Page 114: ...e as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Operand2 to the value in Rn This is the same as an ADDS instruction except that the result is discarded Restrictions In these instructions do not use PC Operand2 must not be SP Condition Flags These instructions update the N Z C and V flags according to the result Examples CMP R2 R9 CMN R0 6400 CMPGT ...

Page 115: ... synonym for LSL S cond Rd Rm Rs MOV S cond Rd Rm LSR Rs is a synonym for LSR S cond Rd Rm Rs MOV S cond Rd Rm ROR Rs is a synonym for ROR S cond Rd Rm Rs See ASR LSL LSR ROR and RRX The MVN instruction takes the value of Operand2 performs a bitwise logical NOT operation on the value and places the result into Rd The MOVW instruction provides the same function as MOV but is restricted to using the...

Page 116: ...n R12 to R10 flags get updated MOV R3 23 Write value of 23 to R3 MOV R8 SP Write value of stack pointer to R8 MVNS R2 0xF Write value of 0xFFFFFFF0 bitwise inverse of 0xF to the R2 and update flags 11 6 5 7 MOVT Move Top Syntax MOVT cond Rd imm16 where Operation MOVT writes a 16 bit immediate value imm16 to the top halfword Rd 31 16 of its destination reg ister The write does not affect Rd 15 0 Th...

Page 117: ...t signed big endian data Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples REV R3 R7 Reverse byte order of value in R7 and write it to R3 REV16 R0 R0 Reverse byte order of each 16 bit halfword in R0 REVSH R0 R5 Reverse Signed Halfword REVHS R3 R7 Reverse with Higher or Same condition RBIT R7 R8 Reverse bit order of value in R8 and writ...

Page 118: ...operand Writes the result in the corresponding bytes of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SADD16 R1 R0 Adds the halfwords in R0 to the corresponding halfwords of R1 and writes to corresponding halfword of R1 SADD8 R4 R0 R5 Adds bytes of R0 to the corresponding byte in R5 and writes to the corres...

Page 119: ...each byte of the first operand to the corresponding byte of the second operand 2 Shuffles the result by one bit to the right halving the data 3 Writes the byte results in the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SHADD16 R1 R0 Adds halfwords in R0 to corresponding halfword of R1 and writes halved result...

Page 120: ... addition to the bottom halfword of the destination regis ter shifted by one bit to the right causing a divide by two or halving 3 Adds the bottom halfword of the first operand with the top halfword of the second operand 4 Writes the halfword result of the division in the top halfword of the destination register shifted by one bit to the right causing a divide by two or halving Restrictions Do not...

Page 121: ...tination register The SHSUBB8 instruction 1 Subtracts each byte of the second operand from the corresponding byte of the first operand 2 Shuffles the result by one bit to the right halving the data 3 Writes the corresponding signed byte results in the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SHSUB16 R1 R0 ...

Page 122: ...e of the first operand 2 Writes the difference result of four signed bytes in the corresponding byte of the desti nation register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SSUB16 R1 R0 Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword of R1 SSUB8 R4 R0 R5 Subtracts bytes of R5 from...

Page 123: ... the bottom halfword of the destination register 3 Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand 4 Writes the signed result of the subtraction to the top halfword of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the condition code flags Examples SASX R0 R4 R5 Adds top ...

Page 124: ... is the same as the EORS instruction except that it discards the result Use the TEQ instruction to test if two values are equal without affecting the V or C flags TEQ is also useful for testing the sign of a value After the comparison the N flag is the logical Exclusive OR of the sign bits of the two operands Restrictions Do not use SP and do not use PC Condition Flags These instructions update th...

Page 125: ...cond operand 2 writes the unsigned result in the corresponding byte of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples UADD16 R1 R0 Adds halfwords in R0 to corresponding halfword of R1 writes to corresponding halfword of R1 UADD8 R4 R0 R5 Adds bytes of R0 to corresponding byte in R5 and writes to correspondin...

Page 126: ...ord of the destination register 3 Subtracts the bottom halfword of the second operand from the top halfword of the first operand 4 Writes the unsigned result from the subtraction to the top halfword of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the condition code flags Examples UASX R0 R4 R5 Adds top halfword of R4 to bott...

Page 127: ...es the byte result by one bit to the right halving the data 3 Writes the unsigned results in the corresponding byte in the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples UHADD16 R7 R3 Adds halfwords in R7 to corresponding halfword of R3 and writes halved result to corresponding halfword in R7 UHADD8 R4 R0 R5 Add...

Page 128: ...ation register 4 Adds the bottom halfword of the first operand with the top halfword of the second operand 5 Shifts the result by one bit to the right causing a divide by two or halving 6 Writes the halfword result of the addition to the bottom halfword of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the condition code flags...

Page 129: ... result by one bit to the right halving the data 3 Writes the unsigned byte results to the corresponding byte of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples UHSUB16 R1 R0 Subtracts halfwords in R0 from corresponding halfword of R1 and writes halved result to corresponding halfword in R1 UHSUB8 R4 R0 R5 Su...

Page 130: ...value of each bit of APSR GE 2 Depending on the value of APSR GE assigns the destination register the value of either the first or second operand register Restrictions None Condition Flags These instructions do not change the flags Examples SADD16 R0 R1 R2 Set GE bits based on result SEL R0 R0 R3 Select bytes from R0 or R3 based on GE c q is a standard assembler syntax fields Rd is the destination...

Page 131: ...her 3 Writes the result to the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples USAD8 R1 R4 R0 Subtracts each byte in R0 from corresponding byte of R4 adds the differences and writes to R1 USAD8 R0 R5 Subtracts bytes of R5 from corresponding byte in R0 adds the differences and writes to R0 cond is an optional cond...

Page 132: ...nces 4 Writes the result to the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples USADA8 R1 R0 R6 Subtracts bytes in R0 from corresponding halfword of R1 adds differences adds value of R6 writes to R1 USADA8 R4 R0 R5 R2 Subtracts bytes of R5 from corresponding byte in R0 adds differences adds value of R2 writes to ...

Page 133: ...ach byte of the second operand register from the corresponding byte of the first operand register 2 Writes the unsigned byte result in the corresponding byte of the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples USUB16 R1 R0 Subtracts halfwords in R0 from corresponding halfword of R1 writes to corresponding half...

Page 134: ...SMLALDX Signed Multiply Accumulate Long Dual SMLAW B T Signed Multiply Accumulate word by halfword SMLSD Signed Multiply Subtract Dual SMLSLD Signed Multiply Subtract Long Dual SMMLA Signed Most Significant Word Multiply Accumulate SMMLS SMMLSR Signed Most Significant Word Multiply Subtract SMUAD SMUADX Signed Dual Multiply Add SMUL B T Signed Multiply word by halfword SMMUL SMMULR Signed Most Sig...

Page 135: ... signed or unsigned Restrictions In these instructions do not use SP and do not use PC If the S suffix is used with the MUL instruction Rd Rn and Rm must all be in the range R0 to R7 Rd must be the same as Rm the cond suffix must not be used Condition Flags If S is specified the MUL instruction updates the N and Z flags according to the result does not affect the C and V flags Examples MUL R10 R2 ...

Page 136: ...sult to RdLo The UMLAL instruction multiplies the two unsigned integers in the first and second operands Adds the 64 bit result to the 64 bit unsigned integer contained in RdHi and RdLo Writes the result back to RdHi and RdLo Restrictions In these instructions do not use SP and do not use PC RdHi and RdLo must be different registers Condition Flags These instructions do not affect the condition co...

Page 137: ...n sets the Q flag in the APSR No overflow can occur during the multiplication Restrictions In these instructions do not use SP and do not use PC Condition Flags If an overflow is detected the Q flag is set op is one of SMLA Signed Multiply Accumulate Long halfwords X and Y specifies which half of the source registers Rn and Rm are used as the first and second multiply operand If X is B then the bo...

Page 138: ...plies top halfwords of R6 and R4 adds R1 and writes the sum to R5 SMLABT R5 R6 R4 R1 Multiplies bottom halfword of R6 with top halfword of R4 adds R1 and writes to R5 SMLABT R4 R3 R2 Multiplies bottom halfword of R4 with top halfword of R3 adds R2 and writes to R4 SMLAWB R10 R2 R5 R3 Multiplies R2 with bottom halfword of R5 adds R3 to the result and writes top 32 bits to R10 SMLAWT R10 R2 R1 R5 Mu...

Page 139: ...cation and addition to Rd Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SMLAD R10 R2 R1 R5 Multiplies two halfword values in R2 with corresponding halfwords in R1 adds R5 and writes to R10 SMLALDX R0 R2 R4 R6 Multiplies top halfword of R2 with bottom halfword of R4 multiplies bottom halfword of R2 with top halfword of R4 adds R6 an...

Page 140: ...p signed halfword of Rm and the bottom signed halfword values of Rn with the bottom signed halfword of Rm Or if X is present multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and the bottom signed halfword values of Rn with the top signed halfword of Rm op is one of SMLAL Signed Multiply Accumulate Long SMLAL Signed Multiply Accumulate Long halfwords X and Y X and ...

Page 141: ...R2 SMLALD R6 R8 R5 R1 Multiplies top halfwords in R5 and R1 and bottom halfwords of R5 and R1 adds R8 R6 and writes to R8 R6 SMLALDX R6 R8 R5 R1 Multiplies top halfword in R5 with bottom halfword of R1 and bottom halfword of R5 with top halfword of R1 adds R8 R6 and writes to R8 R6 11 6 6 6 SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op X cond Rd Rn...

Page 142: ...ction Writes the 64 bit result of the addition to the RdHi and RdLo Restrictions In these instructions Do not use SP and do not use PC Condition Flags This instruction sets the Q flag if the accumulate operation overflows Overflow cannot occur during the multiplications or subtraction For the Thumb instruction set these instructions do not affect the condition code flags Examples SMLSD R0 R4 R5 R6...

Page 143: ... in Rn and Rm Optionally rounds the result by adding 0x80000000 Extracts the most significant 32 bits of the result Subtracts the extracted value of the result from the value in Ra Writes the result of the subtraction in Rd Restrictions In these instructions Do not use SP and do not use PC Condition Flags These instructions do not affect the condition code flags op is one of SMMLA Signed Most Sign...

Page 144: ...ruction Multiplies the values from Rn and Rm Optionally rounds the result otherwise truncates the result Writes the most significant signed 32 bits of the result in Rd Restrictions In this instruction do not use SP and do not use PC Condition Flags This instruction does not affect the condition code flags Examples SMULL R0 R4 R5 Multiplies R4 and R5 truncates top 32 bits and writes to R0 SMULLR R6...

Page 145: ... the halfwords of the second operand Performs two signed 16 16 bit multiplications Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication Writes the result of the subtraction to the destination register Restrictions In these instructions Do not use SP and do not use PC Condition Flags Sets the Q flag if the addition overflows The multiplicatio...

Page 146: ...nd Rm as four signed 16 bit integers These instructions Multiplies the specified signed halfword Top or Bottom values from Rn and Rm Writes the 32 bit result of the multiplication in Rd The SMULWT and SMULWB instructions interprets the values from Rn as a 32 bit signed integer and Rm as two halfword 16 bit signed integers These instructions op is one of SMUL XY Signed Multiply halfwords X and Y sp...

Page 147: ... R4 with the top halfword of R5 multiplies results and writes to R0 SMULBB R0 R4 R5 Multiplies the bottom halfword of R4 with the bottom halfword of R5 multiplies results and writes to R0 SMULTT R0 R4 R5 Multiplies the top halfword of R4 with the top halfword of R5 multiplies results and writes to R0 SMULTB R0 R4 R5 Multiplies the top halfword of R4 with the bottom halfword of R5 multiplies result...

Page 148: ...ies these integers and places the least significant 32 bits of the result in RdLo and the most significant 32 bits of the result in RdHi The SMLAL instruction interprets the values from Rn and Rm as two s complement signed integers It multiplies these integers adds the 64 bit result to the 64 bit signed integer contained in RdHi and RdLo and writes the result back to RdHi and RdLo Restrictions In ...

Page 149: ...m For both instructions if the value in Rn is not divisible by the value in Rm the result is rounded towards zero Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SDIV R0 R2 R4 Signed divide R0 R2 R4 UDIV R8 R8 R1 Unsigned divide R8 R8 R1 cond is an optional condition code see Conditional Execution Rd is the destination register If Rd...

Page 150: ...t is called saturation If satura tion occurs the instruction sets the Q flag to 1 in the APSR Otherwise it leaves the Q flag unchanged To clear the Q flag to 0 the MSR instruction must be used see MSR To read the state of the Q flag the MRS instruction must be used see MRS Table 11 22 Saturating Instructions Mnemonic Description SSAT Signed Saturate SSAT16 Signed Saturate Halfword USAT Unsigned Sa...

Page 151: ...on occurs these instructions set the Q flag to 1 Examples SSAT R7 16 R7 LSL 4 Logical shift left value in R7 by 4 then saturate it as a signed 16 bit value and write it back to R7 USATNE R0 7 R5 Conditionally saturate value in R5 as an unsigned 7 bit value and write it to R0 op is one of SSAT Saturates a signed value to a signed range USAT Saturates a signed value to an unsigned range cond is an o...

Page 152: ...tion register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the condition code flags If saturation occurs these instructions set the Q flag to 1 Examples SSAT16 R7 9 R2 Saturates the top and bottom highwords of R2 as 9 bit values writes to corresponding halfword of R7 USAT16NE R0 13 R5 Conditionally saturates the top and bottom halfwords of R5 as 13 ...

Page 153: ...ave the Q flag unchanged To clear the Q flag to 0 the MSR instruction must be used see MSR To read the state of the Q flag the MRS instruction must be used see MRS Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the condition code flags If saturation occurs these instructions set the Q flag to 1 Examples QADD16 R7 R4 R2 Adds halfwords of R4 with corres...

Page 154: ...e results of the sum and writes a 16 bit signed integer in the range 215 x 215 1 where x equals 16 to the top halfword of the destination register The QSAX instruction 1 Subtracts the bottom halfword of the second operand from the top highword of the first operand 2 Adds the bottom halfword of the source operand with the top halfword of the second operand 3 Saturates the results of the sum and wri...

Page 155: ...cond operand value Adds the result of the doubling to the signed saturated value in the first operand Writes the result to the destination register The QDSUB instruction Doubles the second operand value Subtracts the doubled value from the signed saturated value in the first operand Writes the result to the destination register Both the doubling and the addition or subtraction have their results s...

Page 156: ... 16 bit unsigned integer in the range 0 x 216 1 where x equals 16 to the bottom halfword of the destination register The UQSAX instruction 1 Subtracts the bottom halfword of the second operand from the top highword of the first operand 2 Adds the bottom halfword of the first operand with the top halfword of the second operand 3 Saturates the result of the subtraction and writes a 16 bit unsigned i...

Page 157: ...fwords of the first and second operands Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 x 216 1 where x is 16 The UQADD8 instruction Adds each respective byte of the first and second operands Saturates the result of the addition for each byte in the destination register to the unsigned range 0 x 28 1 where x is 8 The UQSUB16 instruction S...

Page 158: ...R3 R0 Subtracts halfwords in R0 from corresponding halfword in R3 saturates to 16 bits writes to corresponding halfword in R6 UQSUB8 R1 R5 R6 Subtracts bytes in R6 from corresponding byte of R5 saturates to 8 bits writes to corresponding byte of R1 11 6 8 Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data Table 11 23 Packing and Unp...

Page 159: ...C Condition Flags This instruction does not change the flags Examples PKHBT R3 R4 R5 LSL 0 Writes bottom halfword of R4 to bottom halfword of R3 writes top halfword of R5 unshifted to top halfword of R3 PKHTB R4 R0 R2 ASR 1 Writes R2 shifted right by 1 bit to bottom halfword of R4 and writes top halfword of R0 to top halfword of R4 op is one of PKHBT Pack Halfword bottom and top with shift PKHTB P...

Page 160: ...ot use PC Condition Flags These instructions do not affect the flags Examples SXTH R4 R6 ROR 16 Rotates R6 right by 16 bits obtains bottom halfword of result sign extends to 32 bits and writes to R4 UXTB R3 R10 Extracts lowest byte of value in R10 zero extends and writes to R3 op is one of SXTB Sign extends an 8 bit value to a 32 bit value SXTH Sign extends a 16 bit value to a 32 bit value SXTB16 ...

Page 161: ...6 bits 3 Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in Rd Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the flags op is one of SXTAB Sign extends an 8 bit value to a 32 bit value and add SXTAH Sign extends a 16 bit value to a 32 bit value and add SXTAB16 Sign extends two 8 bit values to tw...

Page 162: ...b Other bits in Rd are unchanged BFI copies a bitfield into one register from another register It replaces width bits in Rd starting at the low bit position lsb with width bits from Rn starting at bit 0 Other bits in Rd are unchanged Restrictions Do not use SP and do not use PC Table 11 24 Packing and Unpacking Instructions Mnemonic Description BFC Bit Field Clear BFI Bit Field Insert SBFX Signed ...

Page 163: ...ts a bitfield from one register zero extends it to 32 bits and writes the result to the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the flags Examples SBFX R0 R1 20 4 Extract bit 20 to bit 23 4 bits from R1 and sign extend to 32 bits and then write the result to R0 UBFX R8 R11 9 10 Extract bit 9 to bit 18 10 bits from R11 and z...

Page 164: ... PC Condition Flags These instructions do not affect the flags Examples SXTH R4 R6 ROR 16 Rotate R6 right by 16 bits then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4 UXTB R3 R10 Extract lowest byte of the value in R10 and zero extend it and write the result to R3 extend is one of B Extends an 8 bit value to a 32 bit value H Extends a 16 bit va...

Page 165: ... outside an IT block All other branch instructions must be conditional inside an IT block and must be unconditional out side the IT block see IT Table 11 25 Branch and Control Instructions Mnemonic Description B Branch BL Branch with Link BLX Branch indirect with Link BX Branch indirect CBNZ Compare and Branch if Non Zero CBZ Compare and Branch if Zero IT If Then TBB Table Branch Byte TBH Table Br...

Page 166: ...t has a longer branch range when it is inside an IT block Condition Flags These instructions do not change the flags Examples B loopA Branch to loopA BLE ng Conditionally branch to label ng B W target Branch to target within 16MB range BEQ target Conditionally branch to target BEQ W target Conditionally branch to target within 1MB BL funC Branch with link Call to function funC return address store...

Page 167: ...se equivalent to CMP Rn 0 BEQ label CBNZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BNE label Restrictions The restrictions are Rn must be in the range of R0 to R7 the branch destination must be within 4 to 130 bytes after the instruction these instructions must not be used inside an IT block Condition Flags These instructions do not change the flags Examples ...

Page 168: ... even if its condition fails Exceptions can be taken between an IT instruction and the corresponding IT block or within an IT block Such an exception results in entry to the appropriate exception handler with suitable return information in LR and stacked PSR Instructions designed for use for exception returns can be used as normal to return from the exception and execution of the IT block resumes ...

Page 169: ...g the use of assembler directives within them Condition Flags This instruction does not change the flags Example ITTE NE Next 3 instructions are conditional ANDNE R0 R0 R1 ANDNE does not update condition flags ADDSNE R2 R2 1 ADDSNE updates condition flags MOVEQ R2 R3 Conditional move CMP R0 9 Convert R0 hex value 0 to 15 into ASCII 0 9 A F ITE GT Next 2 instructions are conditional ADDGT R1 R0 55 ...

Page 170: ...inside an IT block it must be the last instruction of the IT block Condition Flags These instructions do not change the flags Examples ADR W R0 BranchTable_Byte TBB R0 R1 R1 is the index R0 is the base address of the branch table Case1 an instruction sequence follows Case2 an instruction sequence follows Case3 an instruction sequence follows BranchTable_Byte DCB 0 Case1 offset calculation DCB Case...

Page 171: ...remaining Cortex M4 instructions Table 11 27 Miscellaneous Instructions Mnemonic Description BKPT Breakpoint CPSID Change Processor State Disable Interrupts CPSIE Change Processor State Enable Interrupts DMB Data Memory Barrier DSB Data Synchronization Barrier ISB Instruction Synchronization Barrier MRS Move from special register to register MSR Move from register to special register NOP No Operat...

Page 172: ...ted by the condition specified by the IT instruction Condition Flags This instruction does not change the flags Examples BKPT 0xAB Breakpoint with immediate value set to 0xAB debugger can extract the immediate value by locating it using the PC Note ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other than Semi hosting 11 6 11 2 CPS Change...

Page 173: ...ble interrupts and configurable fault handlers clear PRIMASK CPSIE f Enable interrupts and fault handlers clear FAULTMASK 11 6 11 3 DMB Data Memory Barrier Syntax DMB cond where cond is an optional condition code see Conditional Execution Operation DMB acts as a data memory barrier It ensures that all explicit memory accesses that appear in program order before the DMB instruction are completed be...

Page 174: ...t memory accesses before it complete Condition Flags This instruction does not change the flags Examples DSB Data Synchronisation Barrier 11 6 11 5 ISB Instruction Synchronization Barrier Syntax ISB cond where cond is an optional condition code see Conditional Execution Operation ISB acts as an instruction synchronization barrier It flushes the pipeline of the processor so that all instructions fo...

Page 175: ...ify write sequence for updating a PSR for example to clear the Q flag In process swap code the programmers model state of the process being swapped out must be saved including relevant PSR contents Similarly the state of the process being swapped in must also be restored These operations use MRS in the state saving instruction sequence and MSR in the state restoring instruction sequence Note BASEP...

Page 176: ...ege level Unprivileged software can only access the APSR See Application Program Status Register Privileged software can access all special registers In unprivileged software writes to unallocated or execution state bits in the PSR are ignored Note When the user writes to BASEPRI_MAX the instruction writes to BASEPRI only if either Rn is non zero and the current BASEPRI value is 0 Rn is non zero a...

Page 177: ...dding for example to place the following instruction on a 64 bit boundary Condition Flags This instruction does not change the flags Examples NOP No operation 11 6 11 9 SEV Send Event Syntax SEV cond where cond is an optional condition code see Conditional Execution Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multipro cessor system It also set...

Page 178: ...to an integer in the range 0 255 8 bit value Operation The SVC instruction causes the SVC exception imm is ignored by the processor If required it can be retrieved by the exception handler to determine what service is being requested Condition Flags This instruction does not change the flags Examples SVC 0x32 Supervisor Call SVC handler can extract the immediate value by locating it via the stacke...

Page 179: ... is enabled an event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction If the event register is 1 WFE clears it to 0 and returns immediately For more information see Power Management Condition Flags This instruction does not change the flags Examples WFE Wait for event 11 6 11 12 WFI Wait for Interrupt Syntax WFI cond where cond is an optional condi...

Page 180: ...on 11 10 System Timer SysTick Memory Protection Unit MPU The Memory Protection Unit MPU improves system reliability by defining the memory attributes for different memory regions It provides up to eight different regions and an optional predefined background region See Section 11 11 Memory Protection Unit MPU 11 7 2 Address Map The address map of the Private peripheral bus PPB is In register descr...

Page 181: ...r returns from the ISR the interrupt becomes pending again and the processor must execute its ISR again This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing 11 8 1 1 Hardware and Software Control of Interrupts The Cortex M4 latches all interrupts A peripheral interrupt becomes pending for one of the fol lowing reasons The NVIC detects that the...

Page 182: ...hese functions see the CMSIS documentation To improve software efficiency the CMSIS simplifies the NVIC register presentation In the CMSIS the Set enable Clear enable Set pending Clear pending and Active Bit registers map to arrays of 32 bit integers so that the array ISER 0 to ISER 1 corresponds to the registers ISER0 ISER1 the array ICER 0 to ICER 1 corresponds to the registers ICER0 ICER1 the a...

Page 183: ...e Interrupt Priority Regis ters Table 11 29 shows how the interrupts or IRQ numbers map onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt Note 1 Each array element corresponds to a single NVIC register for example the element ICER 0 corresponds to the ICER0 register Table 11 29 Mapping of interrupts to the interrupt variables Interrupts CMSIS Array Elem...

Page 184: ...ead write 0x00000000 0XE000E200 Interrupt Set pending Register 0 NVIC_ISPR0 Read write 0x00000000 0xE000E21C Interrupt Set pending Register 7 NVIC_ISPR7 Read write 0x00000000 0XE000E280 Interrupt Clear pending Register 0 NVIC_ICPR0 Read write 0x00000000 0xE000E29C Interrupt Clear pending Register 7 NVIC_ICPR7 Read write 0x00000000 0xE000E300 Interrupt Active Bit Register 0 NVIC_IABR0 Read write 0x...

Page 185: ...No effect 1 Enables the interrupt Read 0 Interrupt disabled 1 Interrupt enabled Notes 1 If a pending interrupt is enabled the NVIC activates the interrupt based on its priority 2 If an interrupt is not enabled asserting its interrupt signal changes the interrupt state to pending the NVIC never activates the interrupt regardless of its priority 31 30 29 28 27 26 25 24 SETENA 23 22 21 20 19 18 17 16...

Page 186: ... write Reset 0x000000000 These registers disable interrupts and show which interrupts are enabled CLRENA Interrupt Set enable Write 0 No effect 1 Disables the interrupt Read 0 Interrupt disabled 1 Interrupt enabled 31 30 29 28 27 26 25 24 CLRENA 23 22 21 20 19 18 17 16 CLRENA 15 14 13 12 11 10 9 8 CLRENA 7 6 5 4 3 2 1 0 CLRENA ...

Page 187: ...Interrupt Set pending Write 0 No effect 1 Changes the interrupt state to pending Read 0 Interrupt is not pending 1 Interrupt is pending Notes 1 Writing 1 to an ISPR bit corresponding to an interrupt that is pending has no effect 2 Writing 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending 31 30 29 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEN...

Page 188: ...rupts and show which interrupts are pending CLRPEND Interrupt Clear pending Write 0 No effect 1 removes the pending state from an interrupt Read 0 Interrupt is not pending 1 Interrupt is pending Note Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt 31 30 29 28 27 26 25 24 CLRPEND 23 22 21 20 19 18 17 16 CLRPEND 15 14 13 12 11 10 9 8 CLRPEND 7 6 5 4 3 2 1 0 C...

Page 189: ...00 These registers indicate which interrupts are active ACTIVE Interrupt Active Flags 0 Interrupt is not active 1 Interrupt is active Note A bit reads as one if the status of the corresponding interrupt is active or active and pending 31 30 29 28 27 26 25 24 ACTIVE 23 22 21 20 19 18 17 16 ACTIVE 15 14 13 12 11 10 9 8 ACTIVE 7 6 5 4 3 2 1 0 ACTIVE ...

Page 190: ...ity Byte Offset 1 refers to register bits 15 8 PRI0 Priority 4m Priority Byte Offset 0 refers to register bits 7 0 Notes 1 Each priority field holds a priority value 0 15 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 7 4 of each field bits 3 0 read as zero and ignore writes 2 for more information about the IP 0 to IP 34 interrupt pri...

Page 191: ...Write only Reset 0x000000000 Write to this register to generate an interrupt from software INTID Interrupt ID Interrupt ID of the interrupt to trigger in the range 0 239 For example a value of 0x03 specifies interrupt IRQ3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 INTID 7 6 5 4 3 2 1 0 INTID ...

Page 192: ...1 SCB_SHPR3 registers it can use byte or aligned halfword or word accesses The processor does not support unaligned accesses to system control block registers In a fault handler to determine the true faulting address 1 Read and save the MMFAR or SCB_BFAR value 2 Read the MMARVALID bit in the MMFSR subregister or the BFARVALID bit in the BFSR subregister The SCB_MMFAR or SCB_BFAR address is valid o...

Page 193: ...onfiguration and Control Register SCB_CCR Read write 0x00000200 0xE000ED18 System Handler Priority Register 1 SCB_SHPR1 Read write 0x00000000 0xE000ED1C System Handler Priority Register 2 SCB_SHPR2 Read write 0x00000000 0xE000ED20 System Handler Priority Register 3 SCB_SHPR3 Read write 0x00000000 0xE000ED24 System Handler Control and State Register SCB_SHCSR Read write 0x00000000 0xE000ED28 Config...

Page 194: ... still executing the IT instruction This behavior is called IT folding and it improves the performance However IT folding can cause jitter in looping If a task must avoid jitter set the DISFOLD bit to 1 before executing the task to disable the IT folding DISDEFWBUF Disable Default Write Buffer When set to 1 it disables the write buffer use during default memory map accesses This causes BusFault to...

Page 195: ...menter Implementer code 0x41 ARM Variant Variant number It is the r value in the rnpn product revision identifier 0x0 Revision 0 Constant Reads as 0xF PartNo Part Number of the processor 0xC24 Cortex M4 Revision Revision number It is the p value in the rnpn product revision identifier 0x0 Patch 0 31 30 29 28 27 26 25 24 Implementer 23 22 21 20 19 18 17 16 Variant Constant 15 14 13 12 11 10 9 8 Par...

Page 196: ...g bit Write 0 no effect 1 changes NMI exception state to pending Read 0 NMI exception is not pending 1 NMI exception is pending As NMI is the highest priority exception the processor normally enters the NMI exception handler as soon as it registers a write of 1 to this bit Entering the handler clears this bit to 0 A read of this bit by the NMI exception handler returns 1 only if the NMI signal is ...

Page 197: ...g VECTPENDING Exception number of the highest priority pending enabled exception 0 no pending exceptions Nonzero the exception number of the highest priority pending enabled exception The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the PRIMASK register RETTOBASE Preempted Active Exceptions present or not 0 there are preempted activ...

Page 198: ... Series Preliminary Note When the user writes to the SCB_ICSR register the effect is unpredictable if writing 1 to the PENDSVSET bit and writing 1 to the PENDSVCLR bit writing 1 to the PENDSTSET bit and writing 1 to the PENDSTCLR bit ...

Page 199: ...ust be aligned to the number of exception entries in the vector table Configure the next statement to give the information required for your implementation the statement reminds the user of how to determine the alignment requirement The minimum alignment is 32 words enough for up to 16 interrupts For more interrupts adjust the alignment by rounding up to the next power of two For example if 21 int...

Page 200: ...UP Interrupt Priority Grouping This field determines the split of group priority from subpriority It shows the position of the binary point that splits the PRI_n fields in the Interrupt Priority Registers into separate group priority and subpriority fields The table below shows how the PRIGROUP value controls this split 31 30 29 28 27 26 25 24 VECTKEYSTAT VECTKEY 23 22 21 20 19 18 17 16 VECTKEYSTA...

Page 201: ... a large system reset of all major components except for debug This bit reads as 0 VECTCLRACTIVE Reserved for Debug use This bit reads as 0 When writing to the register write 0 to this bit otherwise the behavior is unpredictable VECTRESET Reserved for Debug use This bit reads as 0 When writing to the register write 0 to this bit otherwise the behavior is unpredictable 0b101 bxx yyyyyy 7 6 5 0 4 64...

Page 202: ...an event the event is registered and affects the next WFE The processor also wakes up on execution of an SEV instruction or an external event SLEEPDEEP Sleep or Deep Sleep Controls whether the processor uses sleep or deep sleep as its low power mode 0 sleep 1 deep sleep SLEEPONEXIT Sleep on exit Indicates sleep on exit when returning from the Handler mode to the Thread mode 0 do not sleep when ret...

Page 203: ...ent BFHFNMIGN Bus Faults Ignored Enables handlers with priority 1 or 2 to ignore data bus faults caused by load and store instructions This applies to the hard fault and FAULTMASK escalated handlers 0 data bus faults caused by load and store instructions cause a lock up 1 handlers running at priority 1 and 2 ignore data bus faults caused by load and store instructions Set this bit to 1 only when t...

Page 204: ... LDRD and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1 USERSETMPEND Enables unprivileged software access to the NVIC_STIR register see Software Trigger Interrupt Register 0 disable 1 enable NONEBASETHRDENA Thread Mode Enable Indicates how the processor enters Thread mode 0 the processor can enter the Thread mode only when no exception is active 1 the processor can...

Page 205: ... and register for each handler are Each PRI_N field is 8 bits wide but the processor implements only bits 7 4 of each field and bits 3 0 read as zero and ignore writes Table 11 32 System Fault Handler Priority Fields Handler Field Register Description Memory management fault MemManage PRI_4 System Handler Priority Register 1 Bus fault BusFault PRI_5 Usage fault UsageFault PRI_6 SVCall PRI_11 Syste...

Page 206: ...SHPR1 Access Read write Reset 0x000000000 PRI_6 Priority Priority of system handler 6 UsageFault PRI_5 Priority Priority of system handler 5 BusFault PRI_4 Priority Priority of system handler 4 MemManage 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PRI_6 15 14 13 12 11 10 9 8 PRI_5 7 6 5 4 3 2 1 0 PRI_4 ...

Page 207: ...inary 11 9 1 10 System Handler Priority Register 2 Name SCB_SHPR2 Access Read write Reset 0x000000000 PRI_11 Priority Priority of system handler 11 SVCall 31 30 29 28 27 26 25 24 PRI_11 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 208: ...rity Register 3 Name SCB_SHPR3 Access Read write Reset 0x000000000 PRI_15 Priority Priority of system handler 15 SysTick exception PRI_14 Priority Priority of system handler 14 PendSV 31 30 29 28 27 26 25 24 PRI_15 23 22 21 20 19 18 17 16 PRI_14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 209: ...MFAULTENA Memory Management Fault Enable 0 Disables the exception 1 Enables the exception SVCALLPENDED SVC Call Pending Read 0 The exception is not pending 1 The exception is pending The user can write to these bits to change the pending status of the exceptions BUSFAULTPENDED Bus Fault Exception Pending Read 0 The exception is not pending 1 The exception is pending Note The user can write to thes...

Page 210: ...t in this register without a correct adjustment to the stacked content can cause the processor to generate a fault exception Ensure that the software writing to this register retains and subsequently restores the current active status Caution After enabling the system handlers to change the value of a bit in this register the user must use a read modify write procedure to ensure that only the requ...

Page 211: ...y management fault exception is active If the user disables a system handler and the corresponding fault occurs the processor treats the fault as a hard fault The user can write to this register to change the pending or active status of system exceptions An OS kernel can write to the active bits to perform a context switch that changes the current exception type ...

Page 212: ...e exception return points to the faulting instruction The processor has loaded the SCB_MMFAR register with the address of the attempted access MUNSTKERR Memory Manager Fault on Unstacking for a Return From Exception This is part of MMFSR Memory Management Fault Status Subregister 0 No unstacking fault 1 Unstack for an exception return has caused one or more access violations This fault is chained ...

Page 213: ...ts the instruction bus error on prefetching an instruction but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction When the processor sets this bit to 1 it does not write a fault address to the BFAR register PRECISERR Precise Data Bus Error This is part of BFSR Bus Fault Status Subregister 0 No precise data bus error 1 A data bus error has occurred and the PC value ...

Page 214: ...fault address 1 SCB_BFAR holds a valid fault address The processor sets this bit to 1 after a bus fault where the address is known Other faults can set this bit to 0 such as a memory management fault occurring later If a bus fault occurs and is escalated to a hard fault because of priority the hard fault handler must set this bit to 0 This pre vents problems if returning to a stacked active bus fa...

Page 215: ...r UNALIGNED Unaligned Access Usage Fault This is part of UFSR Usage Fault Status Subregister 0 No unaligned access fault or unaligned access trapping not enabled 1 The processor has made an unaligned memory access Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR register to 1 See Configuration and Control Register Unaligned LDM STM LDRD and STRD instructions alwa...

Page 216: ...fault See bitfield 31 15 description in Section 11 9 1 13 Note The UFSR bits are sticky This means that as one or more fault occurs the associated bits are set to 1 A bit that is set to 1 is cleared to 0 only by writing 1 to that bit or by a reset The SCB_CFSR register indicates the cause of a memory management fault bus fault or usage fault It is byte accessible The user can access the SCB_CFSR r...

Page 217: ...ause it is disabled 0 No forced hard fault 1 Forced hard fault When this bit is set to 1 the hard fault handler must read the other fault status registers to find the cause of the fault VECTTBL Bus Fault on a Vector Table It indicates a bus fault on a vector table read during an exception processing 0 No bus fault on vector table read 1 Bus fault on vector table read This error is always handled b...

Page 218: ...the memory management fault Notes 1 When an unaligned access faults the address is the actual address that faulted Because a single read or write instruction can be split into multiple aligned accesses the fault address can be any address in the range of the requested access size 2 Flags in the MMFSR subregister indicate the cause of the fault and whether the value in the SCB_MMFAR register is val...

Page 219: ... field holds the address of the location that generated the bus fault Notes 1 When an unaligned access faults the address in the SCB_BFAR register is the one requested by the instruction even if it is not the address of the fault 2 Flags in the BFSR indicate the cause of the fault and whether the value in the SCB_BFAR register is valid See BFSR Bus Fault Status Subregister 31 30 29 28 27 26 25 24 ...

Page 220: ...re uses aligned word accesses to access the SysTick registers The SysTick counter reload and current value are undefined at reset the correct initialization sequence for the SysTick counter is 1 Program the reload value 2 Clear the current value 3 Program the Control and Status register 11 10 1 System Timer SysTick User Interface Table 11 33 System Timer SysTick Register Mapping Offset Register Na...

Page 221: ...oes not assert the SysTick exception request 1 Counting down to zero asserts the SysTick exception request The software can use COUNTFLAG to determine if SysTick has ever counted to zero ENABLE Enables the counter 0 Counter disabled 1 Counter enabled When ENABLE is set to 1 the counter loads the RELOAD value from the SYST_RVR register and then counts down On reaching 0 it sets the COUNTFLAG to 1 a...

Page 222: ... can be any value in the range 0x00000001 0x00FFFFFF A start value of 0 is possible but has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0 The RELOAD value is calculated according to its use For example to generate a multi shot timer with a period of N pro cessor clock cycles use a RELOAD value of N 1 If the SysTick interrupt is required every...

Page 223: ... The SysTick SYST_CVR register contains the current value of the SysTick counter CURRENT Reads return the current value of the SysTick counter A write of any value clears the field to 0 and also clears the SYST_CSR COUNTFLAG bit to 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CURRENT 15 14 13 12 11 10 9 8 CURRENT 7 6 5 4 3 2 1 0 CURRENT ...

Page 224: ...nd ignores writes SKEW It indicates whether the TENMS value is exact 0 TENMS value is exact 1 TENMS value is inexact or not given An inexact TENMS value can affect the suitability of SysTick as a software real time clock TENMS Ten Milliseconds The reload value for 10 ms 100 Hz timing is subject to system clock skew errors If the value reads as zero the calibration value is not known Read as 0x0000...

Page 225: ...ation that is prohibited by the MPU the processor generates a memory management fault This causes a fault exception and might cause the termination of the process in an OS environment In an OS environment the kernel can update the MPU region setting dynamically based on the process to be executed Typically an embedded OS uses the MPU for memory protection The configuration of MPU regions is based ...

Page 226: ... in the range 4 7 Table 11 35 TEX C B and S Encoding TEX C B S Memory Type Shareability Other Attributes b000 0 0 x 1 Strongly ordered Shareable 1 x 1 Device Shareable 1 0 0 Normal Not shareable Outer and inner write through No write allocate 1 Shareable 1 0 Normal Not shareable Outer and inner write back No write allocate 1 Shareable b001 0 0 0 Normal Not shareable 1 Shareable 1 x 1 Reserved enco...

Page 227: ... separate words Simple code to configure one region R1 region number R2 size enable R3 attributes R4 address LDR R0 MPU_RNR 0xE000ED98 MPU region number register STR R1 R0 0x0 Region Number STR R4 R0 0x4 Region Base Address STRH R2 R0 0x8 Region Size and Enable STRH R3 R0 0xA Region Attribute 01 Write back write and read allocate 10 Write through no write allocate 11 Write back no write allocate T...

Page 228: ...he exception entry and exception return mechanisms cause memory barrier behavior The software does not need any memory barrier instructions during an MPU setup because it accesses the MPU through the PPB which is a Strongly Ordered memory region For example if the user wants all of the memory access behavior to take effect immediately after the programming sequence a DSB instruction and an ISB ins...

Page 229: ...ED9C MPU Region Base register STM R0 R1 R2 Region base address region number and VALID bit and Region Attribute Size and Enable 11 11 1 5 Subregions Regions of 256 bytes or more are divided into eight equal sized subregions Set the correspond ing bit in the SRD field of the MPU_RASR field to disable a subregion See MPU Region Attribute and Size Register The least significant bit of SRD controls th...

Page 230: ...stem program the MPU as follows In most microcontroller implementations the share ability and cache policy attributes do not affect the system behavior However using these settings for the MPU regions can make the application code more portable The values given are for typical situations In special systems such as multiprocessor designs or designs with a separate DMA engine the share ability attri...

Page 231: ...A0 MPU Region Attribute and Size Register MPU_RASR Read write 0x00000000 0xE000EDA4 Alias of RBAR see MPU Region Base Address Register MPU_RBAR_A1 Read write 0x00000000 0xE000EDA8 Alias of RASR see MPU Region Attribute and Size Register MPU_RASR_A1 Read write 0x00000000 0xE000EDAC Alias of RBAR see MPU Region Base Address Register MPU_RBAR_A2 Read write 0x00000000 0xE000EDB0 Alias of RASR see MPU ...

Page 232: ...ates the number of supported MPU instruction regions Always contains 0x00 The MPU memory map is unified and is described by the DREGION field DREGION Data Region Indicates the number of supported MPU data regions 0x08 Eight MPU regions SEPARATE Separate Instruction Indicates support for unified or separate instruction and date memory maps 0 unified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I...

Page 233: ...cts as a region number 1 Any region that is defined and enabled has priority over this default map If the MPU is disabled the processor ignores this bit HFNMIENA Hard Fault and NMI Enabled Enables the operation of MPU during hard fault NMI and FAULTMASK handlers When the MPU is enabled 0 MPU is disabled during hard fault NMI and FAULTMASK handlers regardless of the value of the ENABLE bit 1 the MP...

Page 234: ... When the ENABLE bit is set to 0 the system uses the default memory map This has the same memory attributes as if the MPU is not implemented The default memory map applies to accesses from both privileged and unprivileged software When the MPU is enabled accesses to the System Control Space and vector table are always permitted Other areas are accessible based on regions and whether PRIVDEFENA is ...

Page 235: ...BAR and MPU_RASR registers The MPU supports 8 memory regions so the permitted values of this field are 0 7 Normally the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR However the region number can be changed by writing to the MPU_RBAR with the VALID bit set to 1 see MPU Region Base Address Register This write updates the value of the REGION field 31 30...

Page 236: ... the MPU_RASR there is no valid ADDR field In this case the region occupies the complete memory map and the base address is 0x00000000 The base address is aligned to the size of the region For example a 64 KB region must be aligned on a multiple of 64 KB for example at 0x00010000 or 0x00020000 VALID MPU Region Number Valid Write 0 MPU_RNR not changed and the processor updates the base address for ...

Page 237: ... and the region and subregion enable bits XN Instruction Access Disable 0 Instruction fetches enabled 1 Instruction fetches disabled AP Access Permission See Table 11 37 TEX C B Memory Access Attributes See Table 11 35 S Shareable See Table 11 35 SRD Subregion Disable For each bit in this field 0 corresponding sub region is enabled 1 corresponding sub region is disabled See Subregions for more inf...

Page 238: ... 32B corresponding to a SIZE value of 4 The table below gives an example of SIZE values with the corresponding region size and value of N in the MPU_RBAR Note 1 In the MPU_RBAR see MPU Region Base Address Register ENABLE Region Enable Note For information about access permission see MPU Access Permission Attributes SIZE value Region size Value of N 1 Note b00100 4 32 B 5 Minimum permitted size b01...

Page 239: ... that is sent to memory See also Index register Big endian BE Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory See also Byte invariant Endianness Little endian LE Big endian memory Memory in which a byte or halfword at a word aligned address is the most significant byte or halfword within the word at that address a byte at a...

Page 240: ...data concerned Doubleword A 64 bit data item The contents are taken as being an unsigned integer unless otherwise stated Doubleword aligned A data item having a memory address that is divisible by eight Endianness Byte ordering The scheme that determines the order that successive bytes of a data word are stored in memory An aspect of the system s memory mapping See also Little endian LE and Big en...

Page 241: ...rocessor is passed to when an interrupt occurs Interrupt vector One of a number of fixed addresses in low memory or in high memory if high vectors are configured that contains the first instruction of the corresponding interrupt handler Little endian LE Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory See also Big endian BE ...

Page 242: ...hared resources to ensure correct operation without the risk of shared access conflicts Thumb instruction One or two halfwords that specify an operation for a processor to perform Thumb instructions must be halfword aligned Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned For example a word stored at an addre...

Page 243: ...acteristics Debug access to all memory and registers in the system including Cortex M4 register bank when the core is running halted or held in reset Serial Wire Debug Port SW DP and Serial Wire JTAG Debug Port SWJ DP debug access Flash Patch and Breakpoint FPB unit for implementing breakpoints and code patches Data Watchpoint and Trace DWT unit for implementing watchpoints data tracing and system...

Page 244: ... pro gram and viewing core and peripheral registers Figure 12 2 Application Debug Environment Example 12 3 2 Test Environment Figure 12 3 shows a test environment example JTAG Boundary scan Test vectors are sent and interpreted by the tester In this example the board in test is designed using a number of JTAG compliant devices These devices can be connected to form a single scan chain SAM4 Host De...

Page 245: ... Tester Test Adaptor JTAG Probe Table 12 1 Debug and Test Signal List Signal Name Function Type Active Level Reset Test NRST Microcontroller Reset Input Output Low TST Test Select Input SWD JTAG TCK SWCLK Test Clock Serial Wire Clock Input TDI Test Data In Input TDO TRACESWO Test Data Out Trace Asynchronous Data Out Output TMS SWDIO Test Mode Select Serial Wire Input Output Input JTAGSEL JTAG Sele...

Page 246: ...chpoint and Trace ITM Instrumentation Trace Macrocell TPIU Trace Port Interface Unit The debug architecture information that follows is mainly dedicated to developers of SWJ DP Emulators Probes and debugging tool vendors for Cortex M4 based microcontrollers For further details on SWJ DP see the Cortex M4 technical reference manual Figure 12 4 Debug Architecture 12 5 3 Serial Wire JTAG Debug Port S...

Page 247: ...The sequence is Send more than 50 SWCLKTCK cycles with SWDIOTMS 1 Send the 16 bit sequence on SWDIOTMS 0011110011100111 0x3CE7 MSB first Send more than 50 SWCLKTCK cycles with SWDIOTMS 1 12 5 4 FPB Flash Patch Breakpoint The FPB Implements hardware breakpoints Patches code and data from code space to system space The FPB unit contains Two literal comparators for matching against literal loads from...

Page 248: ...amps are emitted relative to packets The ITM contains a 21 bit counter to generate the timestamp 12 5 6 1 How to Configure the ITM The following example describes how to output trace data in asynchronous trace mode Configure the TPIU for asynchronous trace mode refer to Section 12 5 6 3 5 4 3 How to Configure the TPIU Enable the write accesses into the ITM registers by writing 0xC5ACCE55 into the ...

Page 249: ...y the debugging tool 12 5 7 IEEE 1149 1 JTAG Boundary Scan IEEE 1149 1 JTAG Boundary Scan allows pin level access independent of the device packaging technology IEEE 1149 1 JTAG Boundary Scan is enabled when TST is tied to low while JTAGSEL is high during power up and must be kept in this state during the whole boundary scan operation The SAMPLE EXTEST and BYPASS functions are implemented In SWD J...

Page 250: ... 12 Product Part Number MANUFACTURER IDENTITY 11 1 Set to 0x01F Bit 0 Required by IEEE Std 1149 1 Set to 0x1 31 30 29 28 27 26 25 24 VERSION PART NUMBER 23 22 21 20 19 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER MANUFACTURER IDENTITY 7 6 5 4 3 2 1 0 MANUFACTURER IDENTITY 1 Chip Name Chip ID SAM4S 0x05B32 Chip Name JTAG ID Code SAM4S 0x05B3203F ...

Page 251: ...nd processor resets 13 2 Embedded Characteristics Manages all Resets of the System Including External Devices through the NRST Pin Processor Reset Peripheral Set Reset Based on Embedded Power on Cell Reset Source Status Status of the Last Reset Either Software Reset User Reset Watchdog Reset External Reset Signal Shaping 13 3 Block Diagram Figure 13 1 Reset Controller Block Diagram NRST proc_nrese...

Page 252: ...guration of the Reset Con troller is powered with VDDIO so that its configuration is saved as long as VDDIO is on 13 4 2 NRST Manager After power up NRST is an output during the ERSTL time period defined in the RSTC_MR When ERSTL has elapsed the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal The NRST Manager samples the NRST input pin and d...

Page 253: ...liant with potential external devices connected on the system reset As the ERSTL field is within RSTC_MR register which is backed up it can be used to shape the system power up reset for devices requiring a longer startup time than the Slow Clock Oscillator 13 4 3 Brownout Manager The Brownout manager is embedded within the Supply Controller please refer to the product Supply Controller section fo...

Page 254: ...Reset and the Peripheral Reset are asserted The User Reset is left when NRST rises after a two cycle resynchronization time and a 3 cycle processor startup The processor clock is re enabled as soon as NRST is confirmed high When the processor reset signal is released the RSTTYP field of the Status Register RSTC_SR is loaded with the value 0x4 indicating a User Reset The NRST Manager guarantees tha...

Page 255: ...eously EXTRST Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register RSTC_MR The software reset is entered if at least one of these bits is set by the software All these com mands can be performed independently or simultaneously The software reset lasts 3 Slow Clock cycles The internal reset signals are asserted as soon as the register write is p...

Page 256: ...eset signals depends on the WDRPROC bit in WDT_MR If WDRPROC is 0 the Processor Reset and the Peripheral Reset are asserted The NRST line is also asserted depending on the programming of the field ERSTL However the resulting low level on NRST does not result in a User Reset state If WDRPROC 1 only the processor reset is asserted The Watchdog Timer is reset by the proc_nreset signal As the watchdog...

Page 257: ...s impossible because the Watchdog Timer is being reset by the proc_nreset signal A software reset is impossible since the processor reset is being activated When in Software Reset A watchdog event has priority over the current state The NRST has no effect When in Watchdog Reset The processor reset is active and so a Software Reset cannot be programmed A User Reset cannot be entered Only if WDRPROC...

Page 258: ...it The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge URSTS bit A high to low transition of the NRST pin sets the URSTS bit of the RSTC_SR register This transition is also detected on the Master Clock MCK rising edge see Figure 13 7 If the User Reset is disabled URSTEN 0 and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register ...

Page 259: ...ary 13 5 Reset Controller RSTC User Interface Table 13 1 Register Mapping Offset Register Name Access Reset 0x00 Control Register RSTC_CR Write only 0x04 Status Register RSTC_SR Read only 0x0000_0000 0x08 Mode Register RSTC_MR Read write 0x0000 0001 ...

Page 260: ...RST Peripheral Reset 0 No effect 1 If KEY is correct resets the peripherals EXTRST External Reset 0 No effect 1 If KEY is correct asserts the NRST pin and resets the processor and the peripherals KEY System Reset Key Should be written at value 0xA5 Writing any other value in this field aborts the write operation 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 261: ...ters the NRST Pin Level at Master Clock MCK SRCMP Software Reset Command in Progress 0 No software command is being performed by the reset controller The reset controller is ready for a software command 1 A software reset command is being performed by the reset controller The reset controller is busy 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRCMP NRSTL 15 14 13 12 11 10 9 8 RSTTYP 7 6 5 4 3...

Page 262: ...SRTS bit in RSTC_SR at 1 has no effect on rstc_irq 1 USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN 0 ERSTL External Reset Length This field defines the external reset length The external reset is asserted during a time of 2 ERSTL 1 Slow Clock cycles This allows assertion duration to be programmed between 60 µs and 2 seconds KEY Password Should be written at value 0xA5 Writing any other valu...

Page 263: ...triggers an alarm on a programmed value 14 2 Embedded Characteristics 32 bit Free running back up counter Integrates a 16 bit programmable prescaler running on slow clock Alarm Register capable to generate a wake up of the system through the Shut Down Controller 14 3 Block Diagram Figure 14 1 Real time Timer SLCK RTPRES RTTINC ALMS 16 bit Divider 32 bit Counter ALMV CRTV RTT_MR RTT_VR RTT_AR RTT_S...

Page 264: ...ead at any time in the register RTT_VR Real time Value Register As this value can be updated asynchronously from the Master Clock it is advis able to read this register twice at the same value to improve accuracy of the returned value The current value of the counter is compared with the value written in the alarm register RTT_AR Real time Alarm Register If the counter value matches the alarm the ...

Page 265: ...100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 14 2 RTT Counting Prescaler ALMV ALMV 1 0 ALMV 1 0 RTPRES 1 RTT APB cycle read RTT_SR ALMS RTT_SR APB Interface SCLK RTTINC RTT_SR ALMV 2 ALMV 3 APB cycle ...

Page 266: ...T User Interface Table 14 1 Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read write 0x0000_8000 0x04 Alarm Register RTT_AR Read write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read only 0x0000_0000 0x0C Status Register RTT_SR Read only 0x0000_0000 ...

Page 267: ...qual to RTPRES SCLK period ALMIEN Alarm Interrupt Enable 0 The bit ALMS in RTT_SR has no effect on interrupt 1 The bit ALMS in RTT_SR asserts interrupt RTTINCIEN Real time Timer Increment Interrupt Enable 0 The bit RTTINC in RTT_SR has no effect on interrupt 1 The bit RTTINC in RTT_SR asserts interrupt RTTRST Real time Timer Restart 0 No effect 1 Reloads and restarts the clock divider with the new...

Page 268: ...l time Timer Alarm Register Name RTT_AR Address 0x400E1434 Access Read write ALMV Alarm Value Defines the alarm value ALMV 1 compared with the Real time Timer 31 30 29 28 27 26 25 24 ALMV 23 22 21 20 19 18 17 16 ALMV 15 14 13 12 11 10 9 8 ALMV 7 6 5 4 3 2 1 0 ALMV ...

Page 269: ...eal time Timer Value Register Name RTT_VR Address 0x400E1438 Access Read only CRTV Current Real time Value Returns the current value of the Real time Timer 31 30 29 28 27 26 25 24 CRTV 23 22 21 20 19 18 17 16 CRTV 15 14 13 12 11 10 9 8 CRTV 7 6 5 4 3 2 1 0 CRTV ...

Page 270: ... not occurred since the last read of RTT_SR 1 The Real time Alarm occurred since the last read of RTT_SR RTTINC Real time Timer Increment 0 The Real time Timer has not been incremented since the last read of the RTT_SR 1 The Real time Timer has been incremented since the last read of the RTT_SR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTTINC ALMS ...

Page 271: ...lds and configuring the alarm fields are performed by a parallel capture on the 32 bit data bus An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month year century A clock divider calibration circuitry enables to compensate crystal oscillator frequency inaccuracy An RTC output can be programmed to gener...

Page 272: ...M4S Series Preliminary 15 3 Block Diagram Figure 15 1 RTC Block Diagram User Interface 32768 Divider Time Slow Clock SLCK APB Date RTC Interrup Entry Control Interrupt Control Clock Calibration RTCOUT0 RTCOUT1 Wave Generator Alarm ...

Page 273: ...n is critical The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy 15 5 2 Timing The RTC is updated in real time at one second intervals in normal mode for the counters of sec onds at one minute intervals for the counter of minutes and so on Due to the asynchronous operation of the...

Page 274: ...ister to determine the range to be checked 15 5 5 RTC Internal Free Running Counter Error Checking To improve the reliability and security of the RTC a permanent check is performed on the inter nal free running counters to report non BCD or invalid date time values An error is reported by TDERR bit in the status register RTC_SR if an incorrect value has been detected The flag can be cleared by pro...

Page 275: ...is due to the location of the calendar logic circuity downstream for low power consider ations It is highly recommended to prepare all the fields to be updated before entering programming mode In successive update operations the user must wait at least one second after resetting the UPDTIM UPDCAL bit in the RTC_CR Control Register before setting these bits again This is done by waiting for the SEC...

Page 276: ... Sequence Prepare TIme or Calendar Fields Set UPDTIM and or UPDCAL bit s in RTC_CR Read RTC_SR ACKUPD 1 Clear ACKUPD bit in RTC_SCCR Update Time and or Calendar values in RTC_TIMR RTC_CALR Clear UPDTIM and or UPDCAL bit in RTC_CR No Yes Begin End Polling or IRQ if enabled ...

Page 277: ...pment embedding such a reference clock The correction of value must be programmed into the RTC Mode Register RTC_MR and this value is kept as long as the cir cuitry is powered backup area Removing the backup power supply cancels this calibration This room temperature calibration can be further processed by means of the networking capabil ity of the target application To ease the comparison of the ...

Page 278: ...election choices 1 to 4 respectively select 1Hz 32Hz 64Hz and 512Hz 32Hz or 64Hz can drive for example a TN LCD backplane signal while 1Hz can be used to drive a blinking character like for basic time display hour minute on TN LCDs Selection choice 5 provides a toggling signal when the RTC alarm is reached Selection choice 6 provides a copy of the alarm flag so the associated output is set high lo...

Page 279: ... Hz 32 Hz 64 Hz 512 Hz toggle_alarm flag_alarm pulse 0 1 2 3 4 5 6 7 RTC_MR OUT1 RTCOUT0 0 1 Hz 32 Hz 64 Hz 512 Hz toggle_alarm flag_alarm pulse 0 1 2 3 4 5 6 7 RTC_MR OUT0 flag_alarm alarm match event 1 RTC_SCCR ALRCLR alarm match event 2 RTC_SCCR ALRCLR toggle_alarm pulse Tperiod Tperiod Thigh ...

Page 280: ...write 0x0 0x0C Calendar Register RTC_CALR Read write 0x01A11020 0x10 Time Alarm Register RTC_TIMALR Read write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read write 0x01010000 0x18 Status Register RTC_SR Read only 0x0 0x1C Status Clear Command Register RTC_SCCR Write only 0x20 Interrupt Enable Register RTC_IER Write only 0x24 Interrupt Disable Register RTC_IDR Write only 0x28 Interrupt Mask Regis...

Page 281: ...s Calendar counters can be programmed once this bit is set TIMEVSEL Time Event Selection The event that generates the flag TIMEV in RTC_SR Status Register depends on the value of TIMEVSEL CALEVSEL Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CALEVSEL 15 14 13 12 11 10 9 8 TIMEVSEL 7 6 5 4...

Page 282: ... HIGHPPM description HIGHPPM HIGH PPM Correction 0 lower range ppm correction with accurate correction 1 higher range ppm correction with accurate correction If the absolute value of the correction to be applied is lower than 30ppm it is recommended to clear HIGHPPM HIGHPPM set to 1 is recommended for 30 ppm correction and above Formula If HIGHPPM 0 then the clock frequency correction range is fro...

Page 283: ... to 1 the ppm correction is negative OUT0 RTCOUT0 Output Source Selection OUT1 RTCOUT1 Output Source Selection Value Name Description 0 NO_WAVE no waveform stuck at 0 1 FREQ1HZ 1 Hz square wave 2 FREQ32HZ 32 Hz square wave 3 FREQ64HZ 64 Hz square wave 4 FREQ512HZ 512 Hz square wave 5 ALARM_TOGGLE output toggles when alarm flag rises 6 ALARM_FLAG output is a copy of the alarm flag 7 PROG_PULSE duty...

Page 284: ...Pulse TPERIOD Period of the Output Pulse Value Name Description 0 H_31MS 31 2 ms 1 H_16MS 15 6 ms 2 H_4MS 3 91 ms 3 H_976US 976 µs 4 H_488US 488 µs 5 H_122US 122 µs 6 H_30US 30 5 µs 7 H_15US 15 2 µs Value Name Description 0 P_1S 1 second 1 P_500MS 500 ms 2 P_250MS 250 ms 3 P_125MS 125 ms ...

Page 285: ...urrent Minute The range that can be set is 0 59 BCD The lowest four bits encode the units The higher bits encode the tens HOUR Current Hour The range that can be set is 1 12 BCD in 12 hour mode or 0 23 BCD in 24 hour mode AMPM Ante Meridiem Post Meridiem Indicator This bit is the AM PM indicator in 12 hour mode 0 AM 1 PM All non significant bits read zero 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 286: ... Current Month The range that can be set is 01 12 BCD The lowest four bits encode the units The higher bits encode the tens DAY Current Day in Current Week The range that can be set is 1 7 BCD The coding of the number which number represents which day is user defined as it has no effect on the date counter DATE Current Day in Current Month The range that can be set is 01 31 BCD The lowest four bit...

Page 287: ...alarm field corresponding to the BCD coded minute counter MINEN Minute Alarm Enable 0 The minute matching alarm is disabled 1 The minute matching alarm is enabled HOUR Hour Alarm This field is the alarm field corresponding to the BCD coded hour counter AMPM AM PM Indicator This field is the alarm field corresponding to the BCD coded hour counter HOUREN Hour Alarm Enable 0 The hour matching alarm i...

Page 288: ...ed month counter MTHEN Month Alarm Enable 0 The month matching alarm is disabled 1 The month matching alarm is enabled DATE Date Alarm This field is the alarm field corresponding to the BCD coded date counter DATEEN Date Alarm Enable 0 The date matching alarm is disabled 1 The date matching alarm is enabled 31 30 29 28 27 26 25 24 DATEEN DATE 23 22 21 20 19 18 17 16 MTHEN MONTH 15 14 13 12 11 10 9...

Page 289: ... time event is selected in the TIMEVSEL field in RTC_CR Control Register and can be any one of the following events minute change hour change noon midnight day change CALEV Calendar Event 0 NO_CALEVENT No calendar event has occurred since the last clear 1 CALEVENT At least one calendar event has occurred since the last clear The calendar event is selected in the CALEVSEL field in RTC_CR and can be...

Page 290: ...CCLR Second Clear 0 No effect 1 Clears corresponding status flag in the Status Register RTC_SR TIMCLR Time Clear 0 No effect 1 Clears corresponding status flag in the Status Register RTC_SR CALCLR Calendar Clear 0 No effect 1 Clears corresponding status flag in the Status Register RTC_SR TDERRCLR Time and or Date Free Running Error Clear 0 No effect 1 Clears corresponding status flag in the Status...

Page 291: ...d SECEN Second Event Interrupt Enable 0 No effect 1 The second periodic interrupt is enabled TIMEN Time Event Interrupt Enable 0 No effect 1 The selected time event interrupt is enabled CALEN Calendar Event Interrupt Enable 0 No effect 1 The selected calendar event interrupt is enabled TDERREN Time and or Date Error Interrupt Enable 0 No effect 1 The time and date error interrupt is enabled 31 30 ...

Page 292: ...DIS Second Event Interrupt Disable 0 No effect 1 The second periodic interrupt is disabled TIMDIS Time Event Interrupt Disable 0 No effect 1 The selected time event interrupt is disabled CALDIS Calendar Event Interrupt Disable 0 No effect 1 The selected calendar event interrupt is disabled TDERRDIS Time and or Date Error Interrupt Disable 0 No effect 1 The time and date error interrupt is disabled...

Page 293: ...disabled 1 The alarm interrupt is enabled SEC Second Event Interrupt Mask 0 The second periodic interrupt is disabled 1 The second periodic interrupt is enabled TIM Time Event Interrupt Mask 0 The selected time event interrupt is disabled 1 The selected time event interrupt is enabled CAL Calendar Event Interrupt Mask 0 The selected calendar event interrupt is disabled 1 The selected calendar even...

Page 294: ..._CALR Calendar Register 1 RTC_CALR has contained invalid data since it was last programmed NVTIMALR Non valid Time Alarm 0 No invalid data has been detected in RTC_TIMALR Time Alarm Register 1 RTC_TIMALR has contained invalid data since it was last programmed NVCALALR Non valid Calendar Alarm 0 No invalid data has been detected in RTC_CALALR Calendar Alarm Register 1 RTC_CALALR has contained inval...

Page 295: ... features a 12 bit down counter that allows a watchdog period of up to 16 seconds slow clock at 32 768 kHz It can generate a general reset or a processor reset only In addition it can be stopped while the processor is in debug mode or idle mode 16 2 Embedded Characteristics 16 bit key protected only once Programmable Counter Windowed prevents the processor to be in a dead lock on the watchdog acce...

Page 296: ...ure 16 1 Watchdog Timer Block Diagram 0 1 0 set reset read WDT_SR or reset wdt_fault to Reset Controller set reset WDFIEN wdt_int WDT_MR SLCK 1 128 12 bit Down Counter Current Value WDD WDT_MR WDD WDV WDRSTT WDT_MR WDT_CR reload WDUNF WDERR reload write WDT_MR WDT_MR WDRSTEN ...

Page 297: ... effect If an underflow does occur the wdt_fault signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register WDT_MR Moreover the bit WDUNF is set in the Watchdog Status Register WDT_SR To prevent a software deadlock that continuously triggers the Watchdog the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD WDD is defin...

Page 298: ... Jul 12 SAM4S Series Preliminary Figure 16 2 Watchdog Behavior 0 WDV WDD WDT_CR WDRSTT Watchdog Fault Normal behavior Watchdog Error Watchdog Underflow FFF if WDRSTEN is 1 if WDRSTEN is 0 Forbidden Window Permitted Window ...

Page 299: ...nary 16 5 Watchdog Timer WDT User Interface Table 16 1 Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write only 0x04 Mode Register WDT_MR Read write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read only 0x0000_0000 ...

Page 300: ... Address 0x400E1450 Access Write only WDRSTT Watchdog Restart 0 No effect 1 Restarts the Watchdog KEY Password Should be written at value 0xA5 Writing any other value in this field aborts the write operation 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDRSTT ...

Page 301: ...1 a Watchdog fault underflow or error activates the processor reset WDD Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer If the Watchdog Timer value is less than or equal to WDD writing WDT_CR with WDRSTT 1 restarts the timer If the Watchdog Timer value is greater than WDD writing WDT_CR with WDRSTT 1 causes a Watchdog error WDDBGHLT Watchdog Debug Halt 0 The Watch...

Page 302: ...hdog underflow occurred since the last read of WDT_SR 1 At least one Watchdog underflow occurred since the last read of WDT_SR WDERR Watchdog Error 0 No Watchdog error occurred since the last read of WDT_SR 1 At least one Watchdog error occurred since the last read of WDT_SR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDERR WDUNF ...

Page 303: ...ower Mode by Controlling the Embedded Voltage Regulator Generates the Slow Clock SLCK by Selecting Either the 22 42 kHz Low Power RC Oscillator or the 32 kHz Low Power Crystal Oscillator Supports Multiple Wake Up Sources for Exit from Backup Low Power Mode Force Wake Up Pin with Programmable Debouncing 16 Wake Up Inputs with Programmable Debouncing Real Time Clock Alarm Real Time Timer Alarm Suppl...

Page 304: ...Supply PLLA vr_on vr_mode ON out rtc_alarm SLCK rtc_nreset proc_nreset periph_nreset ice_nreset Master Clock MCK SLCK NRST MAINCK PLLACK FSTT0 FSTT15 XIN32 XOUT32 osc32k_xtal_en Slow Clock SLCK osc32k_rc_en VDDIO VDDCORE VDDOUT ADVREF ADx WKUP0 WKUP15 bod_core_on lcore_brown_out RTT rtt_alarm SLCK rtt_nreset XIN XOUT VDDIO VDDIN PIOx USB Transceivers VDDIO DDP DDM MAINCK DACx PLLB PLLBCK Embedded ...

Page 305: ...n a zero power power on reset cell The zero power power on reset allows the SUPC to start properly as soon as the VDDIO voltage becomes valid At startup of the system once the voltage VDDIO is valid and the embedded 32 kHz RC oscilla tor is stabilized the SUPC starts up the core by sequentially enabling the internal Voltage Regulator waiting that the core voltage VDDCORE is valid then releasing th...

Page 306: ...ystal oscillator in bypass mode instead of connecting a crystal In this case the user has to provide the external clock signal on XIN32 The input characteristics of the XIN32 pin are given in the product electrical characteristics section In order to set the bypass mode the OSCBYPASS bit of the Supply Controller Mode Register SUPC_MR needs to be set at 1 17 4 3 Voltage Regulator Control Backup Low...

Page 307: ...er This can be configured by programming the SMSMPL field in SUPC_SMMR Enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consumption respectively by factors of 32 256 or 2048 if the user does not need a con tinuous monitoring of the VDDIO power supply A supply monitor detection can either generate a reset of the core power supply or a wake up of t...

Page 308: ...omes valid and zero power power on reset signal is released a counter is started for 5 slow clock cycles This is the time it takes for the 32 kHz RC oscillator to stabilize After this time the voltage regulator is enabled The core power supply rises and the brownout detector provides the bodcore_in signal as soon as the core voltage VDDCORE is valid This results in releasing the vddcore_nreset sig...

Page 309: ...Supply Monitor Reset The supply monitor is capable of generating a reset of the system This can be enabled by set ting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register SUPC_SMMR If SMRSTEN is set and if a supply monitor detection occurs the vddcore_nreset signal is imme diately activated for a minimum of 1 slow clock cycle Zero Power Power On Reset Cell output 22 42 kHz RC Osc...

Page 310: ...d then released if bodcore_in has been reactivated The BODRSTS bit is set in the Supply Controller Status Reg ister SUPC_SR so that the user can know the source of the last reset Until bodcore_in is deactivated the vddcore_nreset signal remains active 17 4 7 Wake Up Sources The wake up events allow the device to exit backup mode When a wake up event is detected the Supply Controller performs a seq...

Page 311: ...17 4 are latched in the Supply Controller Status Register SUPC_SR This allows the user to identify the source of the wake up however if a new wake up condition occurs the primary information is lost No new wake up can be detected since the primary wake up condition has disappeared 17 4 7 2 Low Power Debouncer Inputs It is possible to generate a waveform RTCOUT0 and RTCOUT1 in all modes including b...

Page 312: ...es to wake up the core can be configured from 2 up to 8 in the LPDBC field of SUPC_WUMR The period of time between 2 samples can be configured by programming the TPERIOD field in the RTC_MR register Power parameters can be adjusted by modifying the period of time in the THIGH field in RTC_MR The wake up polarity of the inputs can be independently configured by writing WKUPT0 and WKUPT1 fields in S...

Page 313: ...PBR The LPDBCCLR bit must be set to 1 in SUPC_MR 17 4 7 3 Clock Alarms The RTC and the RTT alarms can generate a wake up of the core power supply This can be enabled by writing respectively the bits RTCEN and RTTEN to 1 in the Supply Controller Wake Up Mode Register SUPC_WUMR The Supply Controller does not provide any status as the information is available in the User Interface of either the Real ...

Page 314: ... Time Timer RTT 0x50 0x5C Watchdog Tiler WDT 0x60 0x7C Real Time Clock RTC 0x90 0xDC General Purpose Backup Register GPBR Table 17 2 Register Mapping Offset Register Name Access Reset 0x00 Supply Controller Control Register SUPC_CR Write only N A 0x04 Supply Controller Supply Monitor Mode Register SUPC_SMMR Read write 0x0000_0000 0x08 Supply Controller Mode Register SUPC_MR Read write 0x0000_5A00 ...

Page 315: ...rrect asserts vddcore_nreset and stops the voltage regulator XTALSEL Crystal Oscillator Select 0 NO_EFFECT no effect 1 CRYSTAL_SEL if KEY is correct switches the slow clock on the crystal oscillator output KEY Password Should be written to value 0xA5 Writing any other value in this field aborts the write operation 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 316: ...ted when a supply monitor detection occurs SMIEN Supply Monitor Interrupt Enable 0 NOT_ENABLE the SUPC interrupt signal is not affected when a supply monitor detection occurs 1 ENABLE the SUPC interrupt signal is asserted when a supply monitor detection occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SMIEN SMRSTEN SMSMPL 7 6 5 4 3 2 1 0 SMTH Value Name Description 0x0 ...

Page 317: ...NABLE the core brownout detector is enabled 1 DISABLE the core brownout detector is disabled ONREG Voltage Regulator enable 0 ONREG_UNUSED Voltage Regulator is not used 1 ONREG_USED Voltage Regulator is used OSCBYPASS Oscillator Bypass 0 NO_EFFECT no effect Clock selection depends on XTALSEL value 1 BYPASS the 32 KHz XTAL oscillator is selected and is put in bypass mode KEY Password Key Should be ...

Page 318: ...ply LPDBCEN0 Low power Debouncer ENable WKUP0 0 NOT_ENABLE the WKUP0 input pin is not connected with low power debouncer 1 ENABLE the WKUP0 input pin is connected with low power debouncer and can force a core wake up LPDBCEN1 Low power Debouncer ENable WKUP1 0 NOT_ENABLE the WKUP1input pin is not connected with low power debouncer 1 ENABLE the WKUP1 input pin is connected with low power debouncer ...

Page 319: ...riods 5 32768_SCLK WKUPx shall be in its active state for at least 32 768 SLCK periods 6 Reserved Reserved 7 Reserved Reserved Value Name Description 0 DISABLE Disable the low power debouncer 1 2_RTCOUT0 WKUP0 1 in its active state for at least 2 RTCOUT0 periods 2 3_RTCOUT0 WKUP0 1 in its active state for at least 3 RTCOUT0 periods 3 4_RTCOUT0 WKUP0 1 in its active state for at least 4 RTCOUT0 per...

Page 320: ...OW a low level for a period defined by WKUPDBC on the corresponding wake up input forces the wake up of the core power supply 1 HIGH a high level for a period defined by WKUPDBC on the corresponding wake up input forces the wake up of the core power supply 31 30 29 28 27 26 25 24 WKUPT15 WKUPT14 WKUPT13 WKUPT12 WKUPT11 WKUPT10 WKUPT9 WKUPT8 23 22 21 20 19 18 17 16 WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT...

Page 321: ...ut rising edge event has been detected since the last read of the SUPC_SR When the voltage remains below the defined threshold there is no rising edge event at the output of the brownout detec tion cell The rising edge event occurs only when there is a voltage transition below the threshold SMRSTS Supply Monitor Reset Status 0 NO no supply monitor detection has generated a core reset since the las...

Page 322: ...e wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR LPDBCS1 Low Power Debouncer Wake Up Status on WKUP1 0 NO no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR 1 PRESENT at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR WKUPIS0 WKUPIS15 WKUP Input Status 0 to 15 0 ...

Page 323: ...general purpose backup registers 18 2 Embedded Characteristics Eight 32 bit General Purpose Backup Registers 18 3 General Purpose Backup Registers GPBR User Interface Table 18 1 Register Mapping Offset Register Name Access Reset 0x0 General Purpose Backup Register 0 SYS_GPBR0 Read write 0x1C General Purpose Backup Register 7 SYS_GPBR7 Read write ...

Page 324: ...y 18 3 1 General Purpose Backup Register x Name SYS_GPBRx Address 0x400E1490 Access Read write GPBR_VALUE Value of GPBR x 31 30 29 28 27 26 25 24 GPBR_VALUE 23 22 21 20 19 18 17 16 GPBR_VALUE 15 14 13 12 11 10 9 8 GPBR_VALUE 7 6 5 4 3 2 1 0 GPBR_VALUE ...

Page 325: ...ion that informs the system about the Flash organization thus making the software generic 19 2 Embedded Characteristics Interface of the Flash Block with the 32 bit Internal Bus Increases Performance in Thumb2 Mode with 128 bit or 64 bit Wide Memory Interface up to 100 MHz Code loops optimization 128 Lock Bits Each Protecting a Lock Region GPNVMx General purpose GPNVM Bits One by one Lock Bit Prog...

Page 326: ...nt Controller has no effect on its behavior 19 3 2 Interrupt Sources The Enhanced Embedded Flash Controller EEFC interrupt line is connected to the Nested Vectored Interrupt Controller NVIC Using the Enhanced Embedded Flash Controller EEFC interrupt requires the NVIC to be programmed first The EEFC interrupt is generated only on FRDY bit rising Table 19 1 Peripheral IDs Instance ID EFC 6 ...

Page 327: ...used to protect write erase operation on several pages lock region A lock bit is associated with a lock region composed of several pages in the memory plane Several bits that may be set and cleared through the Enhanced Embedded Flash Controller EEFC interface called General Purpose Non Volatile Memory bits GPNVM bits The embedded Flash size the page size the lock regions organization and GPNVM bit...

Page 328: ...er than perfor mance the user can select a 64 bit wide memory access via the FAM bit in the Flash Mode Register EEFC_FMR Please refer to the electrical characteristics section of the product datasheet for more details 19 4 2 2 Code Read Optimization This feature is enabled if the EEFC_FMR register bit SCOD is cleared A system of 2 x 128 bit or 2 x 64 bit buffers is added in order to optimize seque...

Page 329: ...ll Mb0 to the memory cell Mp1 after recognition of a first backward branch the two first flash memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the pro cessor at the next loop iterations Flash Access Buffer 0 128bits Master Clock ARM Request 32 bit XXX Data To ARM Bytes 0 15 Bytes 16 31 Bytes 32 47 Bytes 0 15 Buffer 1 128bits Bytes 32 47 Bytes 0 3 Bytes 4 7 Bytes 8 ...

Page 330: ...is equal to 1 see Figure 19 5 The data read optimization is enabled by default If the bit SCODIS in Flash Mode Register EEFC_FMR is set to 1 this buffer is disabled and the data read is not optimized anymore Note No consecutive data read accesses are mandatory to benefit from this optimization Figure 19 5 Data Read Optimization for FWS 1 Ln Ln 1 Ln 2 Ln 3 Ln 4 Ln 5 L5 L4 L3 L2 L1 L0 B1 B2 B3 B4 B5...

Page 331: ...e STUI command is achieved All the commands are protected by the same keyword which has to be written in the 8 highest bits of the EEFC_FCR register Writing EEFC_FCR with data that does not contain the correct key and or with an invalid com mand has no effect on the whole memory plane but the FCMDE flag is set in the EEFC_FSR register This flag is automatically cleared by a read access to the EEFC...

Page 332: ...he EEFC_FSR register This flag is automatically cleared by a read access to the EEFC_FSR register Figure 19 6 Command State Chart Check if FRDY flag Set No Yes Read Status MC_FSR Write FCMD and PAGENB in Flash Command Register Check if FLOCKE flag Set Check if FRDY flag Set No Read Status MC_FSR Yes Yes Locking region violation No Check if FCMDE flag Set Yes No Bad keyword violation Command Succes...

Page 333: ...ge Programming and the paragraph below the figure Also a page erase can be automatically done before a page write using EWP or EWPL commands After programming the page the whole lock region can be locked to prevent miscellaneous write or erase sequences The lock bit can be automatically set after page programming using WPL or EWPL commands Data to be written are stored in an internal latch buffer ...

Page 334: ...rogrammed in several steps if it has been erased before see Figure 19 7 below Figure 19 7 Example of Partial Page Programming 19 4 3 3 Erase Commands Erase commands are allowed only on unlocked regions Depending on the Flash memory sev eral commands can be used to erase the Flash Erase all memory EA all memory is erased The processor must not fetch code from the Flash memory Erase pages EPA 4 8 16...

Page 335: ...k the corresponding region Flash Error at the end of the programming the EraseVerify test of the Flash memory has failed 19 4 3 4 Lock Bit Protection Lock bits are associated with several pages in the embedded Flash memory plane This defines lock regions in the embedded Flash memory plane They prevent writing erasing protected pages The lock sequence is The Set Lock command SLB and a page number t...

Page 336: ...32 lock bits as long as it is meaningful Extra reads to the EEFC_FRR register return 0 For example if the third bit of the first word read in the EEFC_FRR is set then the third lock region is locked One error can be detected in the EEFC_FSR register after a programming sequence Command Error a bad keyword has been written in the EEFC_FCR register Flash Error at the end of the programming the Erase...

Page 337: ...ster with GGPB The FARG field is meaningless GPNVM bits can be read by the software application in the EEFC_FRR register The first word read corresponds to the 32 first GPNVM bits following reads provide the next 32 GPNVM bits as long as it is meaningful Extra reads to the EEFC_FRR register return 0 For example if the third bit of the first word read in the EEFC_FRR is set then the third GPNVM bit...

Page 338: ... Unique Identifier is ready to be read the FRDY bit in the Flash Programming Status Register EEFC_FSR falls The Unique Identifier is located in the first 128 bits of the Flash memory mapping thus at the address 0x00400000 0x004003FF To stop the Unique Identifier mode the user needs to send the Stop Read unique Identifier command SPUI by writing the Flash Command Register with the SPUI command When...

Page 339: ...he Write User Signature command WUS by writing the Flash Command Register with the WUS command When programming is completed the FRDY bit in the Flash Programming Status Register EEFC_FSR rises If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR the corresponding interrupt line of the NVIC is activated Two errors can be detected in the EEFC_FSR register after this sequence Command...

Page 340: ...egrated within the System Controller with the base address of 0x400E0A00 Table 19 5 Register Mapping Offset Register Name Access Reset State 0x00 EEFC Flash Mode Register EEFC_FMR Read write 0x0400_0000 0x04 EEFC Flash Command Register EEFC_FCR Write only 0x08 EEFC Flash Status Register EEFC_FSR Read only 0x00000001 0x0C EEFC Flash Result Register EEFC_FRR Read only 0x0 0x10 Reserved ...

Page 341: ...on Disable 0 The sequential code optimization is enabled 1 The sequential code optimization is disabled No Flash read should be done during change of this register FAM Flash Access Mode 0 128 bit access in read Mode only to enhance access speed 1 64 bit access in read Mode only to enhance power consumption No Flash read should be done during change of this register CLOE Code Loops Optimization Ena...

Page 342: ...7 26 25 24 FKEY 23 22 21 20 19 18 17 16 FARG 15 14 13 12 11 10 9 8 FARG 7 6 5 4 3 2 1 0 FCMD Erase all command Field is meaningless Erase plane command FARG must be set with a page number that is in the memory plane to be erased Erase sector command FARG must be set with a page number that is in the sector to be erased Erase pages command FARG 15 2 defines the page from which the erase will start ...

Page 343: ... 1 An invalid command and or a bad keyword was were written in the Flash Mode Register EEFC_FMR This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written FLOCKE Flash Lock Error Status 0 No programming erase of at least one locked region has happened since the last read of EEFC_FSR 1 Programming erase of at least one locked region has happened since the last read of EEFC_FSR ...

Page 344: ...nly Offset 0x0C FVALUE Flash Result Value The result of a Flash command is returned in this register If the size of the result is greater than 32 bits then the next resulting value is accessible at the next register read 31 30 29 28 27 26 25 24 FVALUE 23 22 21 20 19 18 17 16 FVALUE 15 14 13 12 11 10 9 8 FVALUE 7 6 5 4 3 2 1 0 FVALUE ...

Page 345: ...programming using a standard gang programmer The parallel interface is fully handshaked and the device is con sidered to be a standard EEPROM Additionally the parallel protocol offers an optimized access to all the embedded Flash functionalities Although the Fast Flash Programming Mode is a dedicated mode for high volume programming this mode is not designed for in situ programming ...

Page 346: ...N0 PGMEN1 0 50MHz VDDIO VDDCORE VDDIO VDDPLL GND GND VDDIO PGMEN2 Table 20 1 Signal Description List Signal Name Function Type Active Level Comments Power VDDIO I O Lines Power Supply Power VDDCORE Core Power Supply Power VDDPLL PLL Power Supply Power GND Ground Ground Clocks XIN Main Clock Input Input 32KHz to 50MHz Test TST Test Mode Select Input High Must be connected to VDDIO PGMEN0 Test Mode ...

Page 347: ... Table 20 1 Signal Description List Continued Signal Name Function Type Active Level Comments Table 20 2 Mode Coding MODE 3 0 Symbol Data 0000 CMDE Command Register 0001 ADDR0 Address Register LSBs 0010 ADDR1 0011 ADDR2 0100 ADDR3 Address Register MSBs 0101 DATA Data Register Default IDLE No register Table 20 3 Command Bit Coding DATA 15 0 Symbol Command Executed 0x0011 READ Read Flash 0x0012 WP W...

Page 348: ...ered A higher frequency on XIN speeds up the programmer handshake 20 2 4 Programmer Handshaking An handshake is defined for read and write operations When the device is ready to start a new operation RDY signal set the programmer starts the handshake by clearing the NCMD signal The handshaking is achieved once NCMD signal is high and RDY is high 20 2 4 1 Write Handshaking For details on the write ...

Page 349: ...mmand and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input NCMD RDY NOE NVALID DATA 7 0 MODE 3 0 1 2 3 4 5 6 7 9 8 ADDR Adress IN Z Data OUT 10 11 X IN 12 13 Table 20 5 Read Handshake Step Programmer Action Device Action DATA I O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Inpu...

Page 350: ...ncreased 20 2 5 2 Flash Write Command This command is used to write the Flash contents The Flash memory plane is organized into several pages Data to be written are stored in a load buffer that corresponds to a Flash memory page The load buffer is automatically flushed to the Flash 9 Sets NOE signal Output 10 Waits for NVALID high Sets DATA bus in input mode X 11 Sets DATA in output mode Sets NVAL...

Page 351: ...lash Full Erase Command This command is used to erase the Flash memory planes All lock regions must be unlocked before the Full Erase command by using the CLB command Otherwise the erase command is aborted and no page is erased 20 2 5 4 Flash Lock Commands Lock bits can be set using WPL or EWPL commands They can also be set by using the Set Lock command SLB With this command several lock bits can ...

Page 352: ...n of the bit mask is set 20 2 5 6 Flash Security Bit Command A security bit can be set using the Set Security Bit command SSE Once the security bit is active the Fast Flash programming is disabled No other command can be run An event on the Erase pin can erase the security bit once the contents of the Flash have been erased Table 20 9 Set and Clear Lock Bit Command Step Handshake Sequence MODE 3 0...

Page 353: ...on The Memory Write command WRAM is optimized for consecutive writes Write handshaking can be chained an internal address buffer is automatically increased Table 20 13 Set Security Bit Command Step Handshake Sequence MODE 3 0 DATA 15 0 1 Write handshaking CMDE SSE 2 Write handshaking DATA 0 Table 20 14 Write Command Step Handshake Sequence MODE 3 0 DATA 15 0 1 Write handshaking CMDE WRAM 2 Write h...

Page 354: ...iminary 20 2 5 8 Get Version Command The Get Version GVE command retrieves the version of the FFPI interface Table 20 15 Get Version Command Step Handshake Sequence MODE 3 0 DATA 15 0 1 Write handshaking CMDE GVE 2 Write handshaking DATA Version ...

Page 355: ... Characteristics Physically addressed and physically tagged L1 data cache set to 2 Kbytes L1 cache line size set to 16 Bytes L1 cache integrates 32 bus master interface Unified Direct mapped cache architecture Unified 4 Way set associative cache architecture Write through cache operations read allocate Round Robin victim selection policy Event Monitoring with one programmable 32 bit counter Config...

Page 356: ...ies Preliminary 21 3 Block Diagram Figure 21 1 Block Diagram Cache Controller METADATA RAM DATA RAM TAG RAM RAM Interface Cortex M Interface Memory Interface Registers Interface Cortex M PPB Cortex M Memory Interface Bus System Memory Bus ...

Page 357: ...the line is no longer valid the replacement counter points to that line Use the following sequence to invalidate one line of cache 1 Disable the cache controller writing 0 to the CEN field of the CMCC_CTRL register 2 Check CSTS field of the CMCC_SR to verify that the cache is successfully disabled 3 Perform an invalidate by line writing the bit set index way in the CMCC_MAINT1 register 4 Enable th...

Page 358: ... CMCC_CTRL Write only 0x00000000 0x0C Cache Status Register CMCC_SR Read only 0x00000000 0x10 0x1C Reserved 0x20 Cache Maintenance Register 0 CMCC_MAINT0 Write only 0x24 Cache Maintenance Register 1 CMCC_MAINT1 Write only 0x28 Cache Monitor Configuration Register CMCC_MCFG Read write 0x00000000 0x2C Cache Monitor Enable Register CMCC_MEN Read write 0x00000000 0x30 Cache Monitor Control Register CM...

Page 359: ...election is not supported 1 Random victim selection is supported LRUP Least Recently Used Policy Supported 0 Least Recently Used Policy is not supported 1 Least Recently Used Policy is supported RRP Random Selection Policy Supported 0 Random Selection Policy is not supported 1 Random Selection Policy is supported WAYNUM Number of Way 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 360: ...ck Down is supported CSIZE Cache Size CLSIZE Cache Size Value Name Description 0 CSIZE_1KB Cache Size 1 KBytes 1 CSIZE_2KB Cache Size 2 KBytes 2 CSIZE_4KB Cache Size 4 KBytes 3 CSIZE_8KB Cache Size 8 KBytes Value Name Description 0 CLSIZE_1KB 4 bytes 1 CLSIZE_2KB 8 bytes 2 CLSIZE_4KB 16 bytes 3 CLSIZE_8KB 32 bytes ...

Page 361: ...disabled 21 5 3 Cache Controller Control Register Name CMCC_CTRL Address 0x4007C008 Access Write only CEN Cache Controller Enable 0 When set to 0 this field disables the cache controller 1 When set to 1 this field enables the cache controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GCLKDIS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ...

Page 362: ...Address 0x4007C00C Access Write only CSTS Cache Controller Status 0 When read as 0 this field indicates that the cache controller is disabled 1 When read as 1 this field indicates that the cache controller is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSTS ...

Page 363: ...aintenance Register 0 Name CMCC_MAINT0 Address 0x4007C020 Access Write only INVALL Cache Controller Invalidate All 0 No effect 1 When set to one this field invalidates all cache entries 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INVALL ...

Page 364: ...d indicates the cache line that is being invalidated WAY Invalidate Way 31 30 29 28 27 26 25 24 WAY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INDEX Value Name Description 0 WAY0 Way 0 is selection for index invalidation 1 WAY1 Way 1 is selection for index invalidation 2 WAY2 Way 2 is selection for index invalidation 3 WAY3 Way 3 is selection for index invalidation ...

Page 365: ...er Name CMCC_MCFG Address 0x4007C028 Access Write only MODE Cache Controller Monitor Counter Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE Value Name Description 0 CYCLE_COUNT cycle counter 1 IHIT_COUNT instruction hit counter 2 DHIT_COUNT data hit counter ...

Page 366: ...r Name CMCC_MEN Address 0x4007C02C Access Write only Reset 0x00002000 MENABLE Cache Controller Monitor Enable 0 When set to 0 the monitor counter is disabled 1 When set to 1 the monitor counter is activated 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MENABLE ...

Page 367: ...r Monitor Control Register Name CMCC_MCTRL Address 0x4007C030 Access Write only Reset 0x00002000 SWRST Monitor 0 No effect 1 When set to 1 this field resets the event counter register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST ...

Page 368: ...che Controller Monitor Status Register Name CMCC_MSR Address 0x4007C034 Access Write only Reset 0x00002000 EVENT_CNT Monitor Event Counter 31 30 29 28 27 26 25 24 EVENT_CNT 23 22 21 20 19 18 17 16 EVENT_CNT 15 14 13 12 11 10 9 8 EVENT_CNT 7 6 5 4 3 2 1 0 EVENT_CNT ...

Page 369: ...ulation Unit CRCCU 22 1 Description The Cyclic Redundancy Check Calculation Unit CRCCU has its own DMA which functions as a Master with the Bus Matrix 22 2 Embedded Characteristics 32 bit cyclic redundancy check automatic calculation CRC calculation between two addresses of the memory ...

Page 370: ... Series Preliminary 22 3 CRCCU Block Diagram Figure 22 1 Block Diagram AHB Layer Context FSM AHB Interface Host Interface Atmel APB Bus AHB SRAM Data Register Addr Register HRDATA HTRANS HSIZE CRC Register Flash External Bus Interface ...

Page 371: ... has a DMA controller that supports programmable CRC memory checks When enabled the DMA channel reads a programmable amount of data and computes CRC on the fly The CRCCU is controlled by two registers TR_ADDR and TR_CTRL which need to be mapped in the internal SRAM The addresses of these two registers are pointed at by the CRCCU_DSCR register TR_ADDR defines the start address of memory area target...

Page 372: ...ared with the last CRC computed If a mismatch occurs an error flag is set and an interrupt is raised if unmasked The CRCCU accesses the memory by single access TRWIDTH size in order not to limit the bandwidth usage of the system but the DIVIDER field of the CRCCU Mode Register can be used to lower it by dividing the frequency of the single accesses In order to compute the CRC for a memory size lar...

Page 373: ...e memory mapped Table 22 2 Transfer Control Register Memory Mapping Offset Register Name Access CRCCU_DSCR 0x0 CRCCU Transfer Address Register TR_ADDR Read write CRCCU_DSCR 0x4 CRCCU Transfer Control Register TR_CTRL Read write CRCCU_DSCR 0xC 0x10 Reserved CRCCU_DSCR 0x10 CRCCU Transfer Reference Register TR_CRC Read write ...

Page 374: ...M4S Series Preliminary 22 6 1 Transfer Address Register Name TR_ADDR Access Read write Reset 0x00000000 ADDR Transfer Address 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 7 6 5 4 3 2 1 0 ADDR ...

Page 375: ...ZE Buffer Transfer Size TRWIDTH Transfer Width Register IEN Context Done Interrupt Enable When set to zero the transfer done status bit is set at the end of the transfer 31 30 29 28 27 26 25 24 IEN TRWIDTH 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 BTSIZE 7 6 5 4 3 2 1 0 BTSIZE TRWIDTH Single Transfer Size 00 BYTE 01 HALFWORD 10 WORD ...

Page 376: ...ference Register Name TR_CRC Access Read write Reset 0x00000000 REFCRC Reference CRC When Compare mode is enabled the checksum is compared with that register 31 30 29 28 27 26 25 24 REFCRC 23 22 21 20 19 18 17 16 REFCRC 15 14 13 12 11 10 9 8 REFCRC 7 6 5 4 3 2 1 0 REFCRC ...

Page 377: ...0x00000000 0x00000018 CRCCU DMA Interrupt Disable Register CRCCU_DMA_IDR Write only 0x00000000 0x0000001C CRCCU DMA Interrupt Mask Register CRCCU_DMA_IMR Read only 0x00000000 0x00000020 CRCCU DMA Interrupt Status Register CRCCU_DMA_ISR Read only 0x00000000 0x0024 0x0030 Reserved 0x00000034 CRCCU Control Register CRCCU_CR Write only 0x00000000 0x00000038 CRCCU Mode Register CRCCU_MR Read write 0x00...

Page 378: ...or Base Address Register Name CRCCU_DSCR Address 0x40044000 Access Read write Reset 0x00000000 DSCR Descriptor Base Address DSCR needs to be aligned with 512 byte boundaries 31 30 29 28 27 26 25 24 DSCR 23 22 21 20 19 18 17 16 DSCR 15 14 13 12 11 10 9 8 DSCR 7 6 5 4 3 2 1 0 ...

Page 379: ...2 CRCCU DMA Enable Register Name CRCCU_DMA_EN Address 0x40044008 Access Write only Reset 0x00000000 DMAEN DMA Enable Register Write one to enable the CRCCU DMA channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAEN ...

Page 380: ...3 CRCCU DMA Disable Register Name CRCCU_DMA_DIS Address 0x4004400C Access Write only Reset 0x00000000 DMADIS DMA Disable Register Write one to disable the DMA channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMADIS ...

Page 381: ...A Status Register Name CRCCU_DMA_SR Address 0x40044010 Access Read only Reset 0x00000000 DMASR DMA Status Register When set to one this bit indicates that DMA Channel is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMASR ...

Page 382: ...DMA Interrupt Enable Register Name CRCCU_DMA_IER Address 0x40044014 Access Write only Reset 0x00000000 DMAIER Interrupt Enable register Set bit to one to enable the interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAIER ...

Page 383: ...DMA Interrupt Disable Register Name CRCCU_DMA_IDR Address 0x40044018 Access Write only Reset 0x00000000 DMAIDR Interrupt Disable register Set to one to disable the interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAIDR ...

Page 384: ...Name CRCCU_DMA_IMR Address 0x4004401C Access Write only Reset 0x00000000 DMAIMR Interrupt Mask Register 0 Buffer Transfer Completed interrupt is disabled 1 Buffer Transfer Completed interrupt is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAIMR ...

Page 385: ...egister Name CRCCU_DMA_ISR Address 0x40044020 Access Read only Reset 0x00000000 DMAISR Interrupt Status register When DMAISR is set DMA buffer transfer has terminated This flag is reset after read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAISR ...

Page 386: ...trol Register Name CRCCU_CR Address 0x40044034 Access Write only Reset 0x00000000 RESET CRC Computation Reset When set to one this bit resets the CRCCU_SR register to 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET ...

Page 387: ...r If a mismatch occurs the ERRISR bit in the CRCCU_ISR register is set PTYPE Primitive Polynomial DIVIDER Request Divider CRCCU DMA performs successive transfers It is possible to reduce the bandwidth drained by the CRCCU DMA by pro gramming the DIVIDER field The transfer request frequency is divided by 2 DIVIDER 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 388: ... CRCCU_SR Address 0x4004403C Access Read only Reset 0x00000000 CRC Cyclic Redundancy Check Value This register can not be read if the COMPARE field of the CRC_MR register is set to true 31 30 29 28 27 26 25 24 CRC 23 22 21 20 19 18 17 16 CRC 15 14 13 12 11 10 9 8 CRC 7 6 5 4 3 2 1 0 CRC ...

Page 389: ...liminary 22 7 12 CRCCU Interrupt Enable Register Name CRCCU_IER Address 0x40044040 Access Write only Reset 0x00000000 ERRIER CRC Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRIER ...

Page 390: ...iminary 22 7 13 CRCCU Interrupt Disable Register Name CRCCU_IDR Address 0x40044044 Access Write only Reset 0x00000000 ERRIDR CRC Error Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRIDR ...

Page 391: ...reliminary 22 7 14 CRCCU Interrupt Mask Register Name CRCCU_IMR Address 0x40044048 Access Write only Reset 0x00000000 ERRIMR CRC Error Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRIMR ...

Page 392: ...eliminary 22 7 15 CRCCU Interrupt Status Register Name CRCCU_ISR Address 0x4004404C Access Read only Reset 0x00000000 ERRISR CRC Error Interrupt Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRISR ...

Page 393: ...z 16 000 MHz 18 432 MHz UART0 requirements None Note 1 Must be 2500 ppm and 1 2V Square Wave Signal 23 3 Flow Diagram The Boot Program implements the algorithm in Figure 23 1 Figure 23 1 Boot Program Algorithm Flow Diagram The SAM BA Boot program seeks to detect a source clock either from the embedded main oscil lator with external crystal main oscillator enabled or from a supported frequency sign...

Page 394: ...ack setup 2 Setup the Embedded Flash Controller 3 External Clock detection crystal or external clock on XIN 4 If external crystal or clock with supported frequency allow USB activation 5 Else does not allow USB activation and use internal 12 MHz RC oscillator 6 Main oscillator frequency detection if no external clock detected 7 Switch Master Clock on Main Oscillator 8 C variable initialization 9 P...

Page 395: ...decimal following by Send a file S Send a file to a specified address Address Address in hexadecimal Output Note There is a time out on this command which is reached when the prompt appears before the end of the command execution Receive a file R Receive data into a file from a specified address Address Address in hexadecimal NbOfBytes Number of bytes in hexadecimal to receive Output Table 23 2 Co...

Page 396: ... size because the Xmodem protocol requires some SRAM memory to work See Section 23 2 Hardware and Software Constraints 23 5 2 Xmodem Protocol The Xmodem protocol supported is the 128 byte length block This protocol uses a two charac ter CRC 16 to guarantee detection of a maximum bit error Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission Each blo...

Page 397: ...lso provides another custom driver used by the SAM BA application atm6124 sys Refer to the document USB Basic Application literature number 6123 for more details 23 5 3 1 Enumeration Process The USB protocol is a master slave protocol This is the host that starts the enumeration send ing requests to the device through the control endpoint The device handles standard requests as defined in the USB ...

Page 398: ...ing while the FRDY bit is not set in the MC_FSR register Since this function is executed from ROM this allows Flash programming such as sector write to be done by code running in Flash The IAP function entry point is retrieved by reading the NMI vector in ROM 0x00800008 This function takes one argument in parameter the command to be sent to the EEFC This function returns the value of the MC_FSR re...

Page 399: ... specific features 24 2 Embedded Characteristics 24 2 1 Matrix Masters The Bus Matrix manages 4 masters which means that each master can perform an access con currently with others to an available slave Each master has its own decoder which is defined specifically for each master In order to sim plify the addressing all the masters have the same decodings 24 2 2 Matrix Slaves The Bus Matrix manage...

Page 400: ...ows to set a default master for every slave At the end of the current access if no other request is pending the slave remains connected to its associated default master A slave can be associated with three kinds of default masters no default master last access master and fixed default master 24 4 1 No Default Master At the end of the current access if no other request is pending the slave is disco...

Page 401: ..._SCFG Each algorithm may be complemented by selecting a default master configuration for each slave When a re arbitration has to be done it is realized only under some specific conditions detailed in the following paragraph 24 5 1 Arbitration Rules Each arbiter has the ability to arbitrate between two or more different master s requests In order to avoid burst breaking and also to provide the maxi...

Page 402: ...iters to dispatch the requests from different masters to the same slave in a round robin manner If two or more master s requests arise at the same time the master with the lowest number is first serviced then the others are serviced in a round robin manner There are three round robin algorithm implemented Round Robin arbitration without default master Round Robin arbitration with last access maste...

Page 403: ... slave the priority of each master may be defined through the Priority Registers for Slaves MATRIX_PRAS and MATRIX_PRBS 24 6 System I O Configuration The System I O Configuration register CCFG_SYSIO allows to configure some I O lines in System I O mode such as JTAG ERASE USB etc or as general purpose I O lines Enabling or disabling the corresponding I O lines in peripheral mode or in PIO mode PIO_...

Page 404: ...RIX_SCFG3 Read write 0x00000010 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read write 0x00000010 0x0054 0x007C Reserved 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read write 0x00000000 0x0084 Reserved 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read write 0x00000000 0x008C Reserved 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read write 0x00000000 0x0094 Reserved 0x...

Page 405: ...th burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst 2 Four Beat Burst The undefined length burst is split into a 4 beat bursts allowing rearbitration at each 4 beat burst end 3 Eight Beat Burst The undefined length burst is split into 8 beat bursts allowing rearbitration at each 8 beat burst end 4 Sixteen Beat Burst The undefined length burst ...

Page 406: ...ss of a burst transfer or for a single access 1 Last Default Master At the end of current slave access if no other master request is pending the slave stays connected to the last master hav ing accessed it This results in not having the one cycle latency when the last master re tries access on the slave again 2 Fixed Default Master At the end of the current slave access if no other master request ...

Page 407: ... Address 0x400E0280 0 0x400E0288 1 0x400E0290 2 0x400E0298 3 0x400E02A0 4 Access Read write MxPR Master x Priority Fixed priority of Master x for accessing the selected slave The higher the number the higher the priority 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 M4PR 15 14 13 12 11 10 9 8 M3PR M2PR 7 6 5 4 3 2 1 0 M1PR M0PR ...

Page 408: ...or TMS SWDIO Assignment 0 TMS SWDIO function selected 1 PB6 function selected SYSIO7 PB7 or TCK SWCLK Assignment 0 TCK SWCLK function selected 1 PB7 function selected SYSIO10 PB10 or DDM Assignment 0 DDM function selected 1 PB10 function selected SYSIO11 PB11 or DDP Assignment 0 DDP function selected 1 PB11 function selected SYSIO12 PB12 or ERASE Assignment 0 ERASE function selected 1 PB12 functio...

Page 409: ...t assigned to a NAND Flash NANDOE and NANWE not used for NCS1 1 NCS1 is assigned to a NAND Flash NANDOE and NANWE used for NCS1 SMC_NFCS2 SMC NAND Flash Chip Select 2 Assignment 0 NCS2 is not assigned to a NAND Flash NANDOE and NANWE not used for NCS2 1 NCS2 is assigned to a NAND Flash NANDOE and NANWE used for NCS2 SMC_NFCS3 SMC NAND Flash Chip Select 3 Assignment 0 NCS3 is not assigned to a NAND...

Page 410: ...if WPKEY corresponds to 0x4D4154 MAT in ASCII 1 Enables the Write Protect if WPKEY corresponds to 0x4D4154 MAT in ASCII Protects the entire MATRIX address space from address offset 0x000 to 0x1FC WPKEY Write Protect KEY Write only Should be written at value 0x4D4154 MAT in ASCII Writing any other value in this field aborts the write operation of the WPEN bit Always reads as 0 31 30 29 28 27 26 25 ...

Page 411: ...Status 0 No Write Protect Violation has occurred since the last write of MATRIX_WPMR 1 At least one Write Protect Violation has occurred since the last write of MATRIX_WPMR WPVSRC Write Protect Violation Source Should be written at value 0x4D4154 MAT in ASCII Writing any other value in this field aborts the write operation of the WPEN bit Always reads as 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 412: ...412 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...

Page 413: ... external devices to extend the current access The SMC is provided with an automatic slow clock mode In slow clock mode it switches from user programmed waveforms to slow rate specific waveforms on read and write signals The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes The External Data Bus can be scrambled unscrambled by means of user keys 25 2 Embedded Ch...

Page 414: ...Level NCS 3 0 Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWE Write Enable Signal Output Low A 23 0 Address Bus Output D 7 0 Data Bus I O NWAIT External Wait Signal Input Low NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low ...

Page 415: ...ement Controller PMC thus the programmer must first configure the PMC to enable the SMC clock 25 5 External Memory Mapping The SMC provides up to 24 address lines A 23 0 This allows each chip select line to address up to 16 Mbytes of memory If the physical memory device connected on one chip select is smaller than 16 Mbytes it wraps around and appears to be repeated within this space The SMC corre...

Page 416: ... register refer to the Bus Matrix User Interface section Access to an external NAND Flash device via the address space reserved to the chip select programmed The user can connect up to 4 NAND Flash devices with separated chip select The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCSx programmed is active NANDOE and NANDWE are dis...

Page 417: ...chip enable CE signal of the device and the ready busy R B signals are connected to PIO lines The CE signal then remains asserted even when NCS3 is not selected preventing the device from returning to standby mode The NANDCS output signal should be used in accordance with the external NAND Flash device type Two types of CE behavior exist depending on the NAND flash device Standard NAND Flash devic...

Page 418: ... 25 4 Standard and CE don t care NAND Flash Application Examples D 7 0 ALE NANDWE NOE NWE A 22 21 CLE AD 7 0 PIO R B SMC CE NAND Flash PIO NCSx Not Connected NANDOE D 7 0 ALE NANDWE NOE NWE A 22 21 CLE AD 7 0 PIO R B SMC CE CE don t care NAND Flash NCSx NANDOE ...

Page 419: ...multiplexed with PIO lines Thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller Configure a PIO line as an input to manage the Ready Busy signal Configure Static Memory Controller CS3 Setup Pulse Cycle and Mode according to NAND Flash timings the data bus width and the system bus frequency In this example the NAND Flash is not addressed as a CE don t care To address ...

Page 420: ...de depending on Flash timings and system bus frequency A21 A1 A0 A2 A3 A4 A5 A6 A7 A8 A15 A9 A12 A13 A11 A10 A14 A16 D6 D0 D3 D4 D2 D1 D5 D7 A17 A20 A18 A19 D 0 7 A 0 21 NRST NWE NCS0 NRD 3V3 3V3 C2 100NF C2 100NF C1 100NF C1 100NF U1 U1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A21 A20 A19 WE RESET WP OE CE VPP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCCQ VSS VSS VCC ...

Page 421: ...ore the NRD falling edge 2 NRD_PULSE the NRD pulse length is the time between NRD falling edge and NRD rising edge 3 NRD_HOLD the NRD hold time is defined as the hold time of address after the NRD rising edge 25 8 1 2 NCS Waveform Similarly the NCS signal can be divided into a setup time pulse length and hold time 1 NCS_RD_SETUP the NCS setup time is defined as the setup time of address before the...

Page 422: ... To ensure that the NRD and NCS timings are coherent user must define the total read cycle instead of the hold timing NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as NRD_HOLD NRD_CYCLE NRD SETUP NRD PULSE NCS_RD_HOLD NRD_CYCLE NCS_RD_SETUP NCS_RD_PULSE 25 8 1 4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and or NCS NRD and NCS remain activ...

Page 423: ...f NRD and turns to Z after the rising edge of NRD In this case the READ_MODE must be set to 1 read is controlled by NRD to indicate that data is available with the rising edge of NRD The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD whatever the programmed wave form of NCS may be Figure 25 7 READ_MODE 1 Data is sampled by SMC before t...

Page 424: ...e NWE falling edge 2 NWE_PULSE The NWE pulse length is the time between NWE falling edge and NWE rising edge 3 NWE_HOLD The NWE hold time is defined as the hold time of address and data after the NWE rising edge 25 8 3 2 NCS Waveforms The NCS signal waveforms in write operation are not the same that those applied in read opera tions but are separately defined 1 NCS_WR_SETUP the NCS setup time is d...

Page 425: ...e that the NWE and NCS timings are coherent the user must define the total write cycle instead of the hold timing This implicitly defines the NWE hold time and NCS write hold times as NWE_HOLD NWE_CYCLE NWE_SETUP NWE_PULSE NCS_WR_HOLD NWE_CYCLE NCS_WR_SETUP NCS_WR_PULSE 25 8 3 4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and or NCS NWE and or NCS remain active contin...

Page 426: ...ip select indi cates which signal controls the write operation 25 8 4 1 Write is Controlled by NWE WRITE_MODE 1 Figure 25 11 shows the waveforms of a write operation with WRITE_MODE set to 1 The data is put on the bus during the pulse and hold steps of the NWE signal The internal data buffers are switched to output mode after the NWE_SETUP time and until the end of the write cycle regardless of th...

Page 427: ... of the write cycle regardless of the programmed waveform on NWE Figure 25 12 WRITE_MODE 0 The write operation is controlled by NCS 25 8 5 Write Protected Registers To prevent any single software error that may corrupt SMC behavior the registers listed below can be write protected by setting the WPEN bit in the SMC Write Protect Mode Register SMC_WPMR If a write access in a write protected registe...

Page 428: ...LE register groups the definition of all cycle parameters NRD_CYCLE NWE_CYCLE Table shows how the timing parameters are coded and their permitted range 25 8 7 Reset Values of Timing Parameters Table 25 2 gives the default value of timing parameters at reset Coding and Range of Timing Parameters Coded Value Number of Bits Effective Value Permitted Range Coded Value Effective Value setup 5 0 6 128 x...

Page 429: ... setup and hold times must be converted into setup and hold times in reference to the address bus 25 9 Scrambling Unscrambling Function The external data bus D 7 0 can be scrambled in order to prevent intellectual property data located in off chip memories from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device The scrambling and unscrambli...

Page 430: ...tically inserted if at least one of the following conditions is valid if the write controlling signal has no hold time and the read controlling signal has no setup time Figure 25 14 in NCS write controlled mode WRITE_MODE 0 if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0 regardless of the read mode Figure 25 15 The write operation must end with a NCS rising ...

Page 431: ... No Setup Figure 25 15 Early Read Wait State NCS Controlled Write with No Hold Followed by a Read with No NCS Setup write cycle Early Read wait state MCK NRD NWE read cycle no setup no hold D 7 0 A 23 0 write cycle WRITE_MODE 0 Early Read wait state MCK NRD NCS read cycle no setup no hold D 7 0 A 23 0 READ_MODE 0 or READ_MODE 1 ...

Page 432: ...e device a Reload Configuration Wait State is inserted even if the change does not concern the current Chip Select 25 10 3 1 User Procedure To insert a Reload Configuration Wait State the SMC detects a write access to any SMC_MODE register of the user interface If the user only modifies timing registers SMC_SETUP SMC_PULSE SMC_CYCLE registers in the user interface he must validate the modification...

Page 433: ...sponding chip select The value of TDF_CYCLES indicates the number of data float wait cycles between 0 and 15 before the external device releases the bus and represents the time allowed for the data output to go to high impedance after the memory is disabled Data float wait states do not delay internal memory accesses Hence a single access to an external memory with long tDF will not slow down the ...

Page 434: ...ptimization Enabled TDF_MODE 1 When the TDF_MODE of the SMC_MODE register is set to 1 TDF optimization is enabled the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert NCS NRD controlled read operation tpacc MCK NRD D 7 0 TDF 2 clock cycles A 23 0 NCS TDF 3 clock cycles tpacc MCK D 7 0 NCS controlled read operation A 23 0 NRD ...

Page 435: ...ion is disabled TDF wait states are inserted at the end of the read transfer so that the data float period is ended when the second access begins If the hold period of the read1 controlling signal overlaps the data float period no additional TDF wait states will be inserted Figure 25 20 Figure 25 21 and Figure 25 22 illustrate the cases Read access followed by a read access on another chip select ...

Page 436: ...YCLES 6 TDF_CYCLES 6 TDF_MODE 0 A 23 0 read1 cycle Chip Select Wait State MCK read1 controlling signal NRD read2 controlling signal NRD D 7 0 read1 hold 1 read 2 cycle read2 setup 1 5 TDF WAIT STATES optimization disabled TDF_CYCLES 4 TDF_CYCLES 4 TDF_MODE 0 optimization disabled A 23 0 read1 cycle Chip Select Wait State Read to Write Wait State MCK read1 controlling signal NRD write2 controlling ...

Page 437: ...tes between read and write accesses on the same chip select TDF_CYCLES 5 TDF_CYCLES 5 TDF_MODE 0 optimization disabled A 23 0 read1 cycle Read to Write Wait State MCK read1 controlling signal NRD write2 controlling signal NWE D 7 0 read1 hold 1 write2 cycle write2 setup 1 4 TDF WAIT STATES ...

Page 438: ... Asynchronous Page Mode on page 446 or in Slow Clock Mode Slow Clock Mode on page 444 The NWAIT signal is assumed to be a response of the external device to the read write request of the SMC Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior 25 12 2 Frozen Mode...

Page 439: ... Write Access with NWAIT Assertion in Frozen Mode EXNW_MODE 10 EXNW_MODE 10 Frozen WRITE_MODE 1 NWE_controlled NWE_PULSE 5 NCS_WR_PULSE 7 A 23 0 MCK NWE NCS 4 3 2 1 1 1 0 1 4 5 6 3 2 2 2 2 1 0 Write cycle D 7 0 NWAIT FROZEN STATE internally synchronized NWAIT signal ...

Page 440: ...IT Assertion in Frozen Mode EXNW_MODE 10 EXNW_MODE 10 Frozen READ_MODE 0 NCS_controlled NRD_PULSE 2 NRD_HOLD 6 NCS_RD_PULSE 5 NCS_RD_HOLD 3 A 23 0 MCK NCS NRD 1 0 4 3 4 3 2 5 5 5 2 2 0 2 1 0 2 1 0 1 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal FROZEN STATE ...

Page 441: ... step of the access is performed This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation If the NWAIT signal is deasserted before the end of the pulse or asserted after the end of the pulse of the controlling read write signal it has no impact on the access length as shown in Fig ure 25 26 Figure 25 25...

Page 442: ...ion in Read Access Ready Mode EXNW_MODE 11 EXNW_MODE 11 Ready mode READ_MODE 0 NCS_controlled NRD_PULSE 7 NCS_RD_PULSE 7 A 23 0 MCK NCS NRD 4 5 6 3 2 0 0 0 1 4 5 6 3 2 1 1 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal Wait STATE Assertion is ignored ...

Page 443: ...ter the hold state of the access without detecting the NWAIT signal assertion This is true in frozen mode as well as in ready mode This is illustrated on Fig ure 25 27 When EXNW_MODE is enabled ready or frozen the user must program a pulse length of the read and write controlling signal of at least minimal pulse length NWAIT latency 2 resynchronization cycles 1 cycle Figure 25 27 NWAIT Latency EXN...

Page 444: ...p selects Table 25 3 indicates the value of read and write parameters in slow clock mode Figure 25 28 Read Write Cycles in Slow Clock Mode 25 13 2 Switching from to Slow Clock Mode to from Normal Mode When switching from slow clock mode to the normal mode the current slow clock mode transfer is completed at high clock rate with the set of slow clock mode parameters See Figure 25 29 on page 445 The...

Page 445: ...CK NWE 1 1 NWE_CYCLE 3 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 1 1 1 2 3 2 NWE_CYCLE 7 NORMAL MODE WRITE Slow clock mode transition is detected Reload Configuration Wait State This write cycle finishes with the slow clock mode set of parameters after the clock rate transition SLOW CLOCK MODE WRITE A 23 0 NCS 1 MCK NWE 1 1 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal...

Page 446: ...n Table 25 4 With page mode memory devices the first access to one page tpa takes longer than the subse quent accesses to the page tsa as shown in Figure 25 31 When in page mode the SMC enables the user to define different read timings for the first access within one page and next accesses within the page Note 1 A denotes the address bus of the memory device 25 14 1 Protocol and Timings in Page Mo...

Page 447: ... the MSB of addresses as defined in Table 25 4 are identical then the cur rent access lies in the same page as the previous one and no page break occurs Using this information all data within the same page sequential or not sequential are accessed with a minimum access time tsa Figure 25 32 illustrates access to an 8 bit memory device in page mode with 8 byte pages Access to D1 causes a page acces...

Page 448: ...100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 25 32 Access to Non Sequential Data within the Same Page A 23 3 A 2 A1 A0 NCS MCK NRD Page address A1 A3 A7 D 7 0 NCS_RD_PULSE NRD_PULSE NRD_PULSE D1 D3 D7 ...

Page 449: ... 25 6 Register Mapping Offset Register Name Access Reset 0x10 x CS_number 0x00 SMC Setup Register SMC_SETUP Read write 0x01010101 0x10 x CS_number 0x04 SMC Pulse Register SMC_PULSE Read write 0x01010101 0x10 x CS_number 0x08 SMC Cycle Register SMC_CYCLE Read write 0x00030003 0x10 x CS_number 0x0C SMC Mode Register SMC_MODE Read write 0x10000003 0x80 SMC OCMS MODE Register SMC_OCMS Read write 0x000...

Page 450: ...n write access the NCS signal setup length is defined as NCS setup length 128 NCS_WR_SETUP 5 NCS_WR_SETUP 4 0 clock cycles NRD_SETUP NRD Setup Length The NRD signal setup length is defined in clock cycles as NRD setup length 128 NRD_SETUP 5 NRD_SETUP 4 0 clock cycles NCS_RD_SETUP NCS Setup Length in READ Access In read access the NCS signal setup length is defined as NCS setup length 128 NCS_RD_SE...

Page 451: ...RD_PULSE NRD Pulse Length In standard read access the NRD signal pulse length is defined in clock cycles as NRD pulse length 256 NRD_PULSE 6 NRD_PULSE 5 0 clock cycles The NRD pulse length must be at least 1 clock cycle In page mode read access the NRD_PULSE parameter defines the duration of the subsequent accesses in the page NCS_RD_PULSE NCS Pulse Length in READ Access In standard read access th...

Page 452: ...setup pulse and hold steps of the NWE and NCS signals It is defined as Write cycle length NWE_CYCLE 8 7 256 NWE_CYCLE 6 0 clock cycles NRD_CYCLE Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle It is equal to the sum of the setup pulse and hold steps of the NRD and NCS signals It is defined as Read cycle length NRD_CYCLE 8 7 256 NRD_CYCLE ...

Page 453: ...es will be inserted after the setup of NWE 0 The write operation is controlled by the NCS signal If TDF optimization is enabled TDF_MODE 1 TDF wait states will be inserted after the setup of NCS EXNW_MODE NWAIT Mode The NWAIT signal is used to extend the current read or write signal It is only taken into account during the pulse phase of the read and write controlling signal When the use of NWAIT ...

Page 454: ...rnaround after the TDF_CYCLES period The external bus cannot be used by another chip select during TDF_CYCLES 1 cycles From 0 up to 15 TDF_CYCLES can be set TDF_MODE TDF Optimization 1 TDF optimization is enabled The number of TDF wait states is optimized using the setup period of the next read write access 0 TDF optimization is disabled The number of TDF wait states is inserted before the next ac...

Page 455: ...crambling for SMC access 25 15 6 SMC OCMS Key1 Register Name SMC_KEY1 Address 0x400E0084 Access Write Once Reset 0x00000000 KEY1 Off Chip Memory Scrambling OCMS Key Part 1 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance the data scrambling depends on KEY1 and KEY2 values 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CS3SE CS2SE CS1SE CS0SE ...

Page 456: ...Once Reset 0x00000000 KEY2 Off Chip Memory Scrambling OCMS Key Part 2 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance the data scrambling depends on KEY2 and KEY1 values 31 30 29 28 27 26 25 24 KEY2 23 22 21 20 19 18 17 16 KEY2 15 14 13 12 11 10 9 8 KEY2 7 6 5 4 3 2 1 0 KEY2 ...

Page 457: ...WPKEY corresponds to 0x534D43 SMC in ASCII Protects the registers listed below Section 25 15 1 SMC Setup Register Section 25 15 2 SMC Pulse Register Section 25 15 3 SMC Cycle Register Section 25 15 4 SMC MODE Register WPKEY Write Protect KEY Should be written at value 0x534D43 SMC in ASCII Writing any other value in this field aborts the write operation of the WPEN bit Always reads as 0 31 30 29 2...

Page 458: ...since the last read of the SMC_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset or code in which a write access has been attempted Note Reading SMC_WPSR automatically clears ...

Page 459: ...verhead by reducing its intervention during the transfer This significantly reduces the number of clock cycles required for a data transfer which improves microcontroller performance To launch a transfer the peripheral triggers its associated PDC channels by using transmit and receive signals When the programmed data is transferred an end of transfer interrupt is gener ated by the peripheral itsel...

Page 460: ...4S Series Preliminary PIOA Receive TWI1 Receive TWI0 Receive UART1 Receive UART0 Receive USART1 Receive USART0 Receive ADC Receive SPI Receive SSC Receive HSMCI Receive Table 26 1 Peripheral DMA Controller Instance Name Channel T R ...

Page 461: ...am Figure 26 1 Block Diagram PDC FULL DUPLEX PERIPHERAL THR RHR PDC Channel A PDC Channel B Control Status Control Control PDC Channel C HALF DUPLEX PERIPHERAL THR Status Control RECEIVE or TRANSMIT PERIPHERAL RHR or THR Control Control RHR PDC Channel D Status Control ...

Page 462: ...d TXBUFE Refer to Section 26 4 3 and to the associated peripheral user interface 26 4 2 Memory Pointers Each full duplex peripheral is connected to the PDC by a receive channel and a transmit chan nel Both channels have 32 bit memory pointers that point respectively to a receive area and to a transmit area in on and or off chip memory Each half duplex peripheral is connected to the PDC by a bidire...

Page 463: ...ads data from memory and puts them to Transmit Holding Register THR of its asso ciated peripheral The same peripheral sends data according to its mechanism 26 4 5 PDC Flags and Peripheral Status Register Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral All these flags are only visible in the Peripheral Status Regis...

Page 464: ... Register PERIPH 1 _RPR Read write 0 0x104 Receive Counter Register PERIPH_RCR Read write 0 0x108 Transmit Pointer Register PERIPH_TPR Read write 0 0x10C Transmit Counter Register PERIPH_TCR Read write 0 0x110 Receive Next Pointer Register PERIPH_RNPR Read write 0 0x114 Receive Next Counter Register PERIPH_RNCR Read write 0 0x118 Transmit Next Pointer Register PERIPH_TNPR Read write 0 0x11C Transm...

Page 465: ... Name PERIPH_RPR Access Read write RXPTR Receive Pointer Register RXPTR must be set to receive buffer address When a half duplex peripheral is connected to the PDC RXPTR TXPTR 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 7 6 5 4 3 2 1 0 RXPTR ...

Page 466: ...r Register RXCTR must be set to receive buffer size When a half duplex peripheral is connected to the PDC RXCTR TXCTR 0 Stops peripheral data transfer to the receiver 1 65535 Starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 7 6 5 4 3 2 1 0 RXCTR ...

Page 467: ...Name PERIPH_TPR Access Read write TXPTR Transmit Counter Register TXPTR must be set to transmit buffer address When a half duplex peripheral is connected to the PDC RXPTR TXPTR 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR ...

Page 468: ... Register TXCTR must be set to transmit buffer size When a half duplex peripheral is connected to the PDC RXCTR TXCTR 0 Stops peripheral data transfer to the transmitter 1 65535 Starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 7 6 5 4 3 2 1 0 TXCTR ...

Page 469: ... Name PERIPH_RNPR Access Read write RXNPTR Receive Next Pointer RXNPTR contains next receive buffer address When a half duplex peripheral is connected to the PDC RXNPTR TXNPTR 31 30 29 28 27 26 25 24 RXNPTR 23 22 21 20 19 18 17 16 RXNPTR 15 14 13 12 11 10 9 8 RXNPTR 7 6 5 4 3 2 1 0 RXNPTR ...

Page 470: ... Register Name PERIPH_RNCR Access Read write RXNCTR Receive Next Counter RXNCTR contains next receive buffer size When a half duplex peripheral is connected to the PDC RXNCTR TXNCTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXNCTR 7 6 5 4 3 2 1 0 RXNCTR ...

Page 471: ... Name PERIPH_TNPR Access Read write TXNPTR Transmit Next Pointer TXNPTR contains next transmit buffer address When a half duplex peripheral is connected to the PDC RXNPTR TXNPTR 31 30 29 28 27 26 25 24 TXNPTR 23 22 21 20 19 18 17 16 TXNPTR 15 14 13 12 11 10 9 8 TXNPTR 7 6 5 4 3 2 1 0 TXNPTR ...

Page 472: ...Register Name PERIPH_TNCR Access Read write TXNCTR Transmit Counter Next TXNCTR contains next transmit buffer size When a half duplex peripheral is connected to the PDC RXNCTR TXNCTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXNCTR 7 6 5 4 3 2 1 0 TXNCTR ...

Page 473: ... peripheral is connected to the PDC disabling the receiver channel requests also disables the transmit ter channel requests TXTEN Transmitter Transfer Enable 0 No effect 1 Enables the PDC transmitter channel requests When a half duplex peripheral is connected to the PDC it enables the transmitter channel requests only if RXTEN is not set It is forbidden to set both TXTEN and RXTEN for a half duple...

Page 474: ...r Transfer Enable 0 PDC Receiver channel requests are disabled 1 PDC Receiver channel requests are enabled TXTEN Transmitter Transfer Enable 0 PDC Transmitter channel requests are disabled 1 PDC Transmitter channel requests are enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXTEN 7 6 5 4 3 2 1 0 RXTEN ...

Page 475: ...tal or Ceramic Resonator based Oscillator which can be bypassed A factory programmed Fast RC Oscillator 3 output frequencies can be selected 4 8 or 12 MHz By default 4MHz is selected Two 80 to 240 MHz programmable PLL input from 3 to 32 MHz capable of providing the clock MCK to the processor and to the peripherals It provides the following clocks SLCK the Slow Clock which is the only permanent clo...

Page 476: ...ADIV2 PLLBDIV2 Power Management Controller Main Clo ck MAINCK PLLA Cloc PLLACK Control Status MOSCSEL Clock G ene rator XIN XOUT XIN32 XOUT32 Sl ow Clock SLCK XTALSEL Supply C ontroller PLLB Cloc PLLBCK 0 1 0 1 3 20 MHz Crystal or Ceramic Resonator Oscilla tor Embedded 4 8 12 MHz Fast RCOscillator 32768 Hz Crystal Oscill ator Embedded 32 kHz RCOscillator ...

Page 477: ...the section DC Characteris tics of the product datasheet Note that the user is not obliged to use the Slow Clock Crystal and can use the RC oscillator instead Figure 27 2 Typical Slow Clock Crystal Oscillator Connection The user can select the crystal oscillator to be the source of the slow clock as it provides a more accurate frequency The command is made by writing the Supply Controller Control ...

Page 478: ... be sure to set the OSCBYPASS bit in the Supply Controller Mode Reg ister SUPC_MR and XTALSEL bit in the Supply Controller Control Register SUPC_CR 27 1 5 Main Clock Figure 27 3 shows the Main Clock block diagram Figure 27 3 Main Clock Block Diagram The Main Clock has two sources 4 8 12 MHz Fast RC Oscillator which starts very quickly and is used at startup 3 to 20 MHz Crystal or Ceramic Resonator...

Page 479: ...r Calibration Register PMC_OCR are the default values set by Atmel during production These values are stored in a specific Flash memory area different from the main memory plane These values cannot be modified by the user and cannot be erased by a Flash erase command or by the ERASE pin Values written by the user s application in PMC_OCR are reset after each power up or peripheral reset 27 1 5 2 4...

Page 480: ...n clock is valid Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor 27 1 5 4 Main Clock Oscillator Selection The user can select either the 4 8 12 MHz Fast RC oscillator or the 3 to 20 MHz Crystal or Ceramic Resonator based oscillator to be the source of Main Clock The advantage of the 4 8 12 MHz Fast RC oscillator is that it provides fast startup time this is why it is s...

Page 481: ...k cycles during 16 periods of Slow Clock so that the frequency of the 4 8 12 MHz Fast RC oscillator or 3 to 20 MHz Crystal or Ceramic Resonator based oscillator can be determined 27 1 6 Divider and PLL Block The device features two Divider PLL Blocks that permit a wide range of frequencies to be selected on either the master clock the processor clock or the programmable clock outputs Additionally ...

Page 482: ...CKB bit in PMC_SR is automatically cleared The values written in the PLLCOUNT field PLLACOUNT PLLBCOUNT in CKGR_PLLR CKGR_PLLAR CKGR_PLLBR are loaded in the PLL counter The PLL counter then decrements at the speed of the Slow Clock until it reaches 0 At this time the LOCK bit is set in PMC_SR and can trigger an interrupt to the pro cessor The user has to load the number of Slow Clock cycles requir...

Page 483: ...Clock programmable from a few hundred Hz to the maximum operating frequency of the device It is available to the modules running permanently such as the Enhanced Embedded Flash Controller Processor Clock HCLK must be switched off when entering the processor in Sleep Mode Free running processor Clock FCLK the Cortex M4 SysTick external clock UDP Clock UDPCK required by USB Device Port operations Pe...

Page 484: ...scilla tor PLLB Clock PLLBCK 0 1 0 1 MCK periph_clk int SLCK MAINCK PLLA CK Prescaler 1 2 3 4 8 16 32 64 HCLK Processor Clock Controller Sleep M ode Master Clock Controller P MC_MCKR Peripherals Clock C ontroller PMC_PCERx ON OFF USB Clock Prescaler 1 2 4 8 16 32 64 pck PLLBCK UDPCK ON OFF FCLK SysTick Divider 8 SLCK MAINCK PLLA CK PLLBCK Processor clock c Free running clock Master clock PLLB and ...

Page 485: ... interrupt to the processor This feature is useful when switching from a high speed clock to a lower one to inform the software when the change is actually done Figure 27 6 Master Clock Controller 27 2 5 Processor Clock Controller The PMC features a Processor Clock Controller HCLK that implements the Processor Sleep Mode The Processor Clock can be disabled by executing the WFI WaitForInterrupt pro...

Page 486: ...ng Peripheral Clock Enable 0 PMC_PCER0 Peripheral Clock Disable 0 PMC_PCDR0 Peripheral Clock Enable 1 PMC_PCER1 and Peripheral Clock Disable 1 PMC_PCDR1 registers The status of the peripheral clock activity can be read in the Peripheral Clock Status Register PMC_PCSR0 and Peripheral Clock Status Register PMC_PCSR1 When a peripheral clock is disabled the clock is immediately stopped The peripheral ...

Page 487: ...he WAITMODE bit at 1 in the PMC Clock Generator Main Oscillator Register CKGR_MOR Waiting for MOSCRCEN bit to be cleared is strongly recommended to ensure that the core will not execute undesired instructions Important Prior to instructing the system to enter in Wait Mode the internal sources of wakeup provided by RTT RTC and USB must be cleared and verified too that none of the enabled external w...

Page 488: ...e CFDEN bit in the PMC Clock Generator Main Oscillator Register CKGR_MOR After reset the detector is disabled However if the 3 to 20 MHz Crystal or Ceramic Resonator based Oscillator is disabled the clock failure detector is disabled too The slow RC oscillator must be enabled The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator Then the status regis...

Page 489: ...CK or PLLBCK A clock failure detection activates a fault output that is connected to the Pulse Width Modulator PWM Controller With this connection the PWM controller is able to force its outputs and to protect the driven device if a clock failure is detected This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Regis te...

Page 490: ...PMC_MCKR The CSS field is used to select the Master Clock divider source By default the selected clock source is main clock The PRES field is used to control the Master Clock prescaler The user can choose between different values 1 2 3 4 8 16 32 64 Master Clock output is prescaler input divided by PRES parameter By default PRES parameter is set to 1 which means that master clock is equal to main c...

Page 491: ...t the Programmable clock divider source Four clock options are available main clock slow clock PLLACK PLLBCK By default the clock source selected is slow clock The PRES field is used to control the Programmable clock prescaler It is possible to choose between different values 1 2 4 8 16 32 64 Programmable clock output is prescaler input divided by PRES parameter By default the PRES parameter is se...

Page 492: ...COUNT designates either PLLACOUNT or PLLBCOUNT Table 27 1 Clock Switching Timings Worst Case From Main Clock SLCK PLL Clock To Main Clock 4 x SLCK 2 5 x Main Clock 3 x PLL Clock 4 x SLCK 1 x Main Clock SLCK 0 5 x Main Clock 4 5 x SLCK 3 x PLL Clock 5 x SLCK PLL Clock 0 5 x Main Clock 4 x SLCK PLLCOUNT x SLCK 2 5 x PLLx Clock 2 5 x PLL Clock 5 x SLCK PLLCOUNT x SLCK 2 5 x PLL Clock 4 x SLCK PLLCOUN...

Page 493: ...ck Switching Waveforms Figure 27 9 Switch Master Clock from Slow Clock to PLLx Clock Figure 27 10 Switch Master Clock from Main Clock to Slow Clock Slow Clock LOCK MCKRDY Master Clock Write PMC_MCKR PLLx Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR ...

Page 494: ...PLLx Programming Figure 27 12 Programmable Clock Output Programming Slow Clock Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Write CKGR_PLLxR PLLx Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PCKx is disabled PCKx is enabled PLL Clock is selected ...

Page 495: ...en attempted The WPVS flag is reset by writing the PMC Write Protect Mode Register PMC_WPMR with the appropriate access key WPKEY The protected registers are PMC System Clock Enable Register PMC System Clock Disable Register PMC Peripheral Clock Enable Register 0 PMC Peripheral Clock Disable Register 0 PMC Clock Generator Main Oscillator Register PMC Clock Generator PLLA Register PMC Clock Generat...

Page 496: ...er PMC_MCKR Read write 0x0000_0001 0x0034 Reserved 0x0038 USB Clock Register PMC_USB Read Write 0x0000_0000 0x003C Reserved 0x0040 Programmable Clock 0 Register PMC_PCK0 Read write 0x0000_0000 0x0044 Programmable Clock 1 Register PMC_PCK1 Read write 0x0000_0000 0x0048 Programmable Clock 2 Register PMC_PCK2 Read write 0x0000_0000 0x004C 0x005C Reserved 0x0060 Interrupt Enable Register PMC_IER Write...

Page 497: ...t listed in the table it must be considered as reserved 0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read only 0x0000_0000 0x010C Reserved 0x0110 Oscillator Calibration Register PMC_OCR Read write 0x0040_4040 Table 27 3 Register Mapping Offset Register Name Access Reset ...

Page 498: ...ten if the WPEN bit is cleared in PMC Write Protect Mode Register UDP USB Device Port Clock Enable 0 No effect 1 Enables the 48 MHz clock UDPCK of the USB Device Port PCKx Programmable Clock x Output Enable 0 No effect 1 Enables the corresponding Programmable Clock output 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP ...

Page 499: ...en if the WPEN bit is cleared in PMC Write Protect Mode Register UDP USB Device Port Clock Disable 0 No effect 1 Disables the 48 MHz clock UDPCK of the USB Device Port PCKx Programmable Clock x Output Disable 0 No effect 1 Disables the corresponding Programmable Clock output 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP ...

Page 500: ... 0 The 48 MHz clock UDPCK of the USB Device Port is disabled 1 The 48 MHz clock UDPCK of the USB Device Port is enabled PCKx Programmable Clock x Output Status 0 The corresponding Programmable Clock output is disabled 1 The corresponding Programmable Clock output is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP ...

Page 501: ...entifiers as defined in the section Peripheral Identifiers in the product datasheet Other peripherals can be enabled in PMC_PCER1 Section 27 2 16 23 PMC Peripheral Clock Enable Register 1 Note Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 1...

Page 502: ...e corresponding peripheral clock Note To get PIDx refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet Other peripherals can be disabled in PMC_PCDR1 Section 27 2 16 24 PMC Peripheral Clock Disable Register 1 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14...

Page 503: ...d Note To get PIDx refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet Other peripherals sta tus can be read in PMC_PCSR1 Section 27 2 16 25 PMC Peripheral Clock Status Register 1 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14...

Page 504: ...lator startup time is achieved MOSCXTBY Main Crystal Oscillator Bypass 0 No effect 1 The Main Crystal Oscillator is bypassed MOSCXTEN must be set to 0 An external clock must be connected on XIN When MOSCXTBY is set the MOSCXTS flag in PMC_SR is automatically set Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag WAITMODE Wait Mode Command 0 No effect 1 Enters the device in Wait ...

Page 505: ...scillator Selection 0 The Main On Chip RC Oscillator is selected 1 The Main Crystal Oscillator is selected CFDEN Clock Failure Detector Enable 0 The Clock Failure Detector is disabled 1 The Clock Failure Detector is enabled Notes 1 The slow RC oscillator must be enabled when the CFDEN is enabled 2 The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator...

Page 506: ...arted by means of RCMEAS 1 The Main Oscillator has been enabled previously and MAINF value is available RCMEAS RC Oscillator Frequency Measure write only 0 No effect 1 Restart a measure of the main RC frequency MAINF will carry the new frequency as soon as a low to high transition occurs on MAINFRDY flag The measure is performed on the main frequency i e not limited to RC oscillator only but if th...

Page 507: ...e Protect Mode Register DIVA Divider 0 Divider output is stuck at 0 1 Divider is bypassed divide by 1 2 up to 255 clock is divided by DIVA PLLACOUNT PLLA Counter Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written MULA PLLA Multiplier 0 The PLLA is deactivated 1 up to 62 The PLLA Clock frequency is the PLLA input frequency multiplied by MU...

Page 508: ... PMC Write Protect Mode Register DIVB Divider 0 Divider output is stuck at 0 1 Divider is bypassed divide by 1 2 up to 255 clock is divided by DIVB PLLBCOUNT PLLB Counter Specifies the number of Slow Clock cycles x8 before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written MULB PLLB Multiplier 0 The PLLB is deactivated 1 up to 62 The PLLB Clock frequency is the PLLB input frequency multipl...

Page 509: ...V2 PLLADIV2 7 6 5 4 3 2 1 0 PRES CSS Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLA Clock is selected 3 PLLB_CLK PLLB Clock is selected Value Name Description 0 CLK_1 Selected clock 1 CLK_2 Selected clock divided by 2 2 CLK_4 Selected clock divided by 4 3 CLK_8 Selected clock divided by 8 4 CLK_16 Selected clock divided by 16 5 CLK_32 Sel...

Page 510: ...510 11100B ATARM 31 Jul 12 SAM4S Series Preliminary PLLBDIV2 PLLB Divisor by 2 PLLBDIV2 PLLB Clock Division 0 PLLB clock frequency is divided by 1 1 PLLB clock frequency is divided by 2 ...

Page 511: ...egister can only be written if the WPEN bit is cleared in PMC Write Protect Mode Register USBS USB Input Clock Selection 0 USB Clock Input is PLLA 1 USB Clock Input is PLLB USBDIV Divider for USB Clock USB Clock is Input clock divided by USBDIV 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 USBDIV 7 6 5 4 3 2 1 0 USBS ...

Page 512: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRES CSS Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLA Clock is selected 3 PLLB_CLK PLLB Clock is selected 4 MCK Master Clock is selected Value Name Description 0 CLK_1 Selected clock 1 CLK_2 Selected clock divided by 2 2 CLK_4 Selected clock divided by 4 3 CLK_8 Selected ...

Page 513: ...PLLB Lock Interrupt Enable MCKRDY Master Clock Ready Interrupt Enable PCKRDYx Programmable Clock Ready x Interrupt Enable MOSCSELS Main Oscillator Selection Status Interrupt Enable MOSCRCS Main On Chip RC Status Interrupt Enable CFDEV Clock Failure Detector Event Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 PCKRDY2 PCKRDY1 PCKRDY0 7 ...

Page 514: ...LB Lock Interrupt Disable MCKRDY Master Clock Ready Interrupt Disable PCKRDYx Programmable Clock Ready x Interrupt Disable MOSCSELS Main Oscillator Selection Status Interrupt Disable MOSCRCS Main On Chip RC Status Interrupt Disable CFDEV Clock Failure Detector Event Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 PCKRDY2 PCKRDY1 PCKRDY...

Page 515: ... Master Clock is ready OSCSELS Slow Clock Oscillator Selection 0 Internal slow clock RC oscillator is selected 1 External slow clock 32 kHz oscillator is selected PCKRDYx Programmable Clock Ready Status 0 Programmable Clock x is not ready 1 Programmable Clock x is ready MOSCSELS Main Oscillator Selection Status 0 Selection is in progress 1 Selection is done MOSCRCS Main On Chip RC Oscillator Statu...

Page 516: ...ne clock failure detection of the main on chip RC oscillator clock has occurred since the last read of PMC_SR CFDS Clock Failure Detector Status 0 A clock failure of the main on chip RC oscillator clock is not detected 1 A clock failure of the main on chip RC oscillator clock is detected FOS Clock Failure Detector Fault Output Status 0 The fault output of the clock failure detector is inactive 1 T...

Page 517: ...B PLLB Lock Interrupt Mask MCKRDY Master Clock Ready Interrupt Mask PCKRDYx Programmable Clock Ready x Interrupt Mask MOSCSELS Main Oscillator Selection Status Interrupt Mask MOSCRCS Main On Chip RC Status Interrupt Mask CFDEV Clock Failure Detector Event Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 ...

Page 518: ... the Power Management Controller RTCAL RTC Alarm Enable 0 The RTC alarm has no effect on the Power Management Controller 1 The RTC alarm enables a fast restart signal to the Power Management Controller USBAL USB Alarm Enable 0 The USB alarm has no effect on the Power Management Controller 1 The USB alarm enables a fast restart signal to the Power Management Controller FLPM Flash Low Power Mode 31 ...

Page 519: ...C Write Protect Mode Register FSTPx Fast Startup Input Polarityx Defines the active polarity of the corresponding wake up input If the corresponding wake up input is enabled and at the FSTP level it enables a fast restart signal 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8 7 6 5 4 3 2 1 0 FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 F...

Page 520: ... 2 16 20 PMC Fault Output Clear Register Name PMC_FOCR Address 0x400E0478 Access Write only FOCLR Fault Output Clear Clears the clock failure detector fault output 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FOCLR ...

Page 521: ...ral Clock Disable Register 0 PMC Clock Generator Main Oscillator Register PMC Clock Generator PLLA Register PMC Clock Generator PLLB Register PMC Master Clock Register PMC USB Clock Register PMC Programmable Clock Register PMC Fast Startup Mode Register PMC Fast Startup Polarity Register PMC Peripheral Clock Enable Register 1 PMC Peripheral Clock Disable Register 1 PMC Oscillator Calibration Regis...

Page 522: ...s occurred since the last read of the PMC_WPSR register If this violation is an unauthor ized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset or code in which a write access has been attempted Reading PMC_WPSR automatically ...

Page 523: ...Mode Register PIDx Peripheral Clock x Enable 0 No effect 1 Enables the corresponding peripheral clock Notes 1 To get PIDx refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet 2 Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 524: ...itten if the WPEN bit is cleared in PMC Write Protect Mode Register on page 521 PIDx Peripheral Clock x Disable 0 No effect 1 Disables the corresponding peripheral clock Note To get PIDx refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID34 PID33 PID32 ...

Page 525: ... only PIDx Peripheral Clock x Status 0 The corresponding peripheral clock is disabled 1 The corresponding peripheral clock is enabled Note To get PIDx refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID34 PID33 PID32 ...

Page 526: ...ld of this register CAL8 RC Oscillator Calibration bits for 8 Mhz Calibration bits applied to the RC Oscillator when SEL8 is set SEL8 Selection of RC Oscillator Calibration bits for 8 Mhz 0 Factory determined value stored in Flash memory 1 Value written by user in CAL8 field of this register CAL12 RC Oscillator Calibration bits for 12 Mhz Calibration bits applied to the RC Oscillator when SEL12 is...

Page 527: ...wired value that is read only The first register con tains the following fields EXT shows the use of the extension identifier register NVPTYP and NVPSIZ identifies the type of embedded non volatile memory and its size ARCH identifies the set of embedded peripherals SRAMSIZ indicates the size of the embedded SRAM EPROC indicates the embedded ARM processor VERSION gives the revision of the silicon T...

Page 528: ...SAM4SD32C 2 1024 160 100 0X29A7_0EE0 SAM4SD32B 2 1024 160 64 0X2997_0EE0 SAM4SD16C 2 512 160 100 0X29A7_0CE0 SAM4SD16B 2 512 160 64 0X2997_0CE0 SAM4SA16C 1024 160 100 0X28A7_0CE0 0x0 SAM4SA16B 1024 160 64 0X2897_0CE0 0x0 SAM4S16B 1024 128 64 0x289C_0CE0 0x0 SAM4S16C 1024 128 100 0x28AC_0CE0 0x0 SAM4S8B 512 128 64 0x289C_0AE0 0x0 SAM4S8C 512 128 100 0x28AC_0AE0 0x0 ...

Page 529: ...2 SAM4S Series Preliminary 28 3 Chip Identifier CHIPID User Interface Table 28 2 Register Mapping Offset Register Name Access Reset 0x0 Chip ID Register CHIPID_CIDR Read only 0x4 Chip ID Extension Register CHIPID_EXID Read only ...

Page 530: ...VPTYP ARCH 23 22 21 20 19 18 17 16 ARCH SRAMSIZ 15 14 13 12 11 10 9 8 NVPSIZ2 NVPSIZ 7 6 5 4 3 2 1 0 EPROC VERSION Value Name Description 1 ARM946ES ARM946ES 2 ARM7TDMI ARM7TDMI 3 CM3 Cortex M3 4 ARM920T ARM920T 5 ARM926EJS ARM926EJS 6 CA5 Cortex A5 7 CM4 Cortex M4 Value Name Description 0 NONE None 1 8K 8K bytes 2 16K 16K bytes 3 32K 32K bytes 4 Reserved 5 64K 64K bytes 6 Reserved 7 128K 128K byt...

Page 531: ... 32K bytes 4 Reserved 5 64K 64K bytes 6 Reserved 7 128K 128K bytes 8 Reserved 9 256K 256K bytes 10 512K 512K bytes 11 Reserved 12 1024K 1024K bytes 13 Reserved 14 2048K 2048K bytes 15 Reserved Value Name Description 0 48K 48K bytes 1 1K 1K bytes 2 2K 2K bytes 3 6K 6K bytes 4 24K 24K bytes 5 4K 4K bytes 6 80K 80K bytes 7 160K 160K bytes 8 8K 8K bytes 9 16K 16K bytes 10 32K 32K bytes 11 64K 64K byte...

Page 532: ...x AT91SAM7Lxx Series 0x75 AT91SAM7Xxx AT91SAM7Xxx Series 0x76 AT91SAM7SLxx AT91SAM7SLxx Series 0x80 SAM3UxC SAM3UxC Series 100 pin version 0x81 SAM3UxE SAM3UxE Series 144 pin version 0x83 SAM3A SAM4A xC SAM3AxC or SAM4AxC Series 100 pin version 0x84 SAM3X SAM4X xC SAM3XxCor SAM4XxC Series 100 pin version 0x85 SAM3X SAM4X xE SAM3XxEor SAM4XxE Series 144 pin version 0x86 SAM3X SAM4X xG SAM3XxGor or ...

Page 533: ...t extension 1 An extended Chip ID exists 0x9A SAM3SDxC SAM3SDxC Series 100 pin version 0xA5 SAM5A SAM5A 0xF0 AT75Cxx AT75Cxx Series Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory 3 ROM_FLASH ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size Value Name Description ...

Page 534: ... 3 2 Chip ID Extension Register Name CHIPID_EXID Address 0x400E0744 Access Read only EXID Chip ID Extension Reads 0 if the bit EXT in CHIPID_CIDR is 0 31 30 29 28 27 26 25 24 EXID 23 22 21 20 19 18 17 16 EXID 15 14 13 12 11 10 9 8 EXID 7 6 5 4 3 2 1 0 EXID ...

Page 535: ...e pull up and pull down of the I O line Input visibility and output control The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation An 8 bit parallel capture mode is also available which can be used to interface a CMOS digital image sensor an ADC a DSP synchronous port in synchronous mode etc 29 2 Embedded Characteristics Up to 32 Pr...

Page 536: ...ts Connection of one Peripheral DMA Controller Channel PDC Which Offers Buffer Reception Without Processor Intervention 29 3 Block Diagram Figure 29 1 Block Diagram Embedded Peripheral Embedded Peripheral PIO Interrupt PIO Controller Parallel Capture Mode Up to 32 pins PMC Up to 32 peripheral IOs Up to 32 peripheral IOs PIO Clock APB Data Enable PIN 31 PIN 1 PIN 0 Data Enable PDC Data Status PIODC...

Page 537: ...ignal Type PIODCCLK Parallel Capture Mode Clock Input PIODC 7 0 Parallel Capture Mode Data Input PIODCEN1 Parallel Capture Mode Data Enable 1 Input PIODCEN2 Parallel Capture Mode Data Enable 2 Input On Chip Peripherals PIO Controller On Chip Peripheral Drivers Control Command Driver Keyboard Driver Keyboard Driver General Purpose I Os External Devices ...

Page 538: ...ls the PIO Controller clock in order to save power Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled This means that the configuration of the I O lines does not require the PIO Controller clock to be enabled However when the clock is disabled not all of the features of the PIO Controller are available including glitch filtering Note that the...

Page 539: ...eading a 1 in PIO_PUSR means the pull up is disabled and reading a 0 means the pull up is enabled The 1 0 1 0 1 0 1 0 D Q D Q DFF 1 0 1 0 11 00 01 10 Programmable Glitch or Debouncing Filter PIO_PDSR 0 PIO_ISR 0 PIO_IDR 0 PIO_IMR 0 PIO_IER 0 PIO Interrupt Up to 32 possible inputs PIO_ISR 31 PIO_IDR 31 PIO_IMR 31 PIO_IER 31 Pad PIO_PUDR 0 PIO_PUSR 0 PIO_PUER 0 PIO_MDDR 0 PIO_MDSR 0 PIO_MDER 0 PIO_C...

Page 540: ...n chip peripheral selected in the PIO_ABCDSR1 and PIO_ABCDSR2 ABCD Select Registers A value of 1 indicates the pin is controlled by the PIO controller If a pin is used as a general purpose I O line not multiplexed with an on chip peripheral PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit After reset most generally the I O lines are controlled by the PIO controlle...

Page 541: ...in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function This enables configura tion of the I O line prior to setting it to be managed by the PIO Controller Similarly writing in PIO_SODR and PIO_CODR effects PIO_ODSR This is important as it defines the first level driven on the I O line 29 5 5 Synchronous Data ...

Page 542: ...ters are independently programmable on each I O line The glitch filter can filter a glitch with a duration of less than 1 2 Master Clock MCK and the debouncing filter can filter a pulse of less than 1 2 Period of a Programmable Divided Slow Clock The selection between glitch filtering or debounce filtering is done by writing in the registers PIO_IFSCDR PIO Input Filter Slow Clock Disable Register ...

Page 543: ...rs are controlled by the register set PIO_IFER Input Filter Enable Register PIO_IFDR Input Filter Disable Register and PIO_IFSR Input Filter Status Register Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR This last register enables the glitch filter on the I O lines When the glitch and or debouncing filter is enabled it does not modify the behavior of the inputs on the ...

Page 544: ...n Additional Interrupt Mode The type of event detection Edge or Level must be selected by writing in the set of registers PIO_ESR Edge Select Register and PIO_LSR Level Select Register which enable respectively the Edge and Level Detection The current status of this selection is accessible through the PIO_ELSR Edge Level Status Register The Polarity of the event detection Rising Falling Edge or Hi...

Page 545: ... writing 32 h0000_00FF in PIO_AIMER 29 5 10 3 Edge or Level Detection Configuration Lines 3 4 and 5 are configured in Level detection by writing 32 h0000_0038 in PIO_LSR The other lines are configured in Edge detection by default if they have not been previously con figured Otherwise lines 0 1 2 6 and 7 must be configured in Edge detection by writing 32 h0000_00C7 in PIO_ESR 29 5 10 4 Falling Risi...

Page 546: ...r can know at anytime which I O line is locked by reading the PIO Lock Status register PIO_LOCKSR Once an I O line is locked the only way to unlock it is to apply a hardware reset to the PIO Controller 29 5 12 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt Trigger By default the Schmitt trigger is active Disabling the Schmitt Trigger is requested when using the...

Page 547: ...thout any intervention from the CPU Transfer status signals from PDC are available in PIO_PCISR through the flags ENDRX and RXBUFF see PIO Parallel Capture Interrupt Status Register on page 587 The parallel capture mode can take into account the sensor data enable signals or not If the bit ALWYS is set to 0 in PIO_PCMR the parallel capture mode samples the sensor data at the ris ing edge of the se...

Page 548: ...RDY OVRE ENDRX and RXBUFF can be a source of the PIO interrupt Figure 29 10 Parallel Capture Mode Waveforms DSIZE 2 ALWYS 0 HALFS 0 Figure 29 11 Parallel Capture Mode Waveforms DSIZE 2 ALWYS 1 HALFS 0 0x23 0x34 0x45 0x12 0x56 0x67 0x78 0x89 0x5645_3423 MCK PIODCCLK PIODC 7 0 PIODCEN1 PIODCEN2 DRDY PIO_PCISR RDATA PIO_PCRHR 0x01 Read of PIO_PCISR 0x23 0x34 0x45 0x12 0x56 0x67 0x78 0x89 0x3423_1201 ...

Page 549: ...l Capture Mode Waveforms DSIZE 2 ALWYS 0 HALFS 1 FRSTS 1 0x23 0x34 0x45 0x12 0x56 0x67 0x78 0x89 0x6745_2301 MCK PIODCCLK PIODC 7 0 PIODCEN1 PIODCEN2 DRDY PIO_PCISR RDATA PIO_PCRHR 0x01 Read of PIO_PCISR 0x23 0x34 0x45 0x12 0x56 0x67 0x78 0x89 0x7856_3412 MCK PIODCCLK PIODC 7 0 PIODCEN1 PIODCEN2 DRDY PIO_PCISR RDATA PIO_PCRHR 0x01 Read of PIO_PCISR ...

Page 550: ...upt Status Register or by waiting the corresponding interrupt 5 Check OVRE flag in PIO_PCISR 6 Read the data in PIO_PCRHR PIO Parallel Capture Reception Holding Register 7 If new data are expected go to step 4 8 Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the previous configuration With PDC 1 Write PIO_PCIDR and PIO_PCIER PIO Parallel Capt...

Page 551: ...iate access key WPKEY The protected registers are PIO Enable Register on page 556 PIO Disable Register on page 556 PIO Output Enable Register on page 557 PIO Output Disable Register on page 558 PIO Input Filter Enable Register on page 559 PIO Input Filter Disable Register on page 559 PIO Multi driver Enable Register on page 564 PIO Multi driver Disable Register on page 565 PIO Pull Up Disable Regi...

Page 552: ...rupt no pull up resistor no glitch filter I O lines 16 to 19 assigned to peripheral A functions with pull up resistor I O lines 20 to 23 assigned to peripheral B functions with pull down resistor I O line 24 to 27 assigned to peripheral C with Input Change Interrupt no pull up resistor and no pull down resistor I O line 28 to 31 assigned to peripheral D no pull up resistor and no pull down resisto...

Page 553: ...d only 0x0000 0000 0x001C Reserved 0x0020 Glitch Input Filter Enable Register PIO_IFER Write only 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write only 0x0028 Glitch Input Filter Status Register PIO_IFSR Read only 0x0000 0000 0x002C Reserved 0x0030 Set Output Data Register PIO_SODR Write only 0x0034 Clear Output Data Register PIO_CODR Write only 0x0038 Output Data Status Register PIO_ODS...

Page 554: ...O_OWSR Read only 0x00000000 0x00AC Reserved 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write only 0x00B4 Additional Interrupt Modes Disables Register PIO_AIMDR Write only 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read only 0x00000000 0x00BC Reserved 0x00C0 Edge Select Register PIO_ESR Write only 0x00C4 Level Select Register PIO_LSR Write only 0x00C8 Edge Level Stat...

Page 555: ...as input changes may have occurred Note if an offset is not listed in the table it must be considered as reserved 0x0110 Reserved 0x0114 0x011C Reserved 0x150 Parallel Capture Mode Register PIO_PCMR Read write 0x00000000 0x154 Parallel Capture Interrupt Enable Register PIO_PCIER Write only 0x158 Parallel Capture Interrupt Disable Register PIO_PCIDR Write only 0x15C Parallel Capture Interrupt Mask ...

Page 556: ...0x400E1204 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 PIO Disable 0 No effect 1 Disables the PIO from controlling the corresponding pin enables peripheral control of the pin 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P...

Page 557: ... 0x400E1210 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Output Enable 0 No effect 1 Enables the output on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P...

Page 558: ...me PIO_OSR Address 0x400E0E18 PIOA 0x400E1018 PIOB 0x400E1218 PIOC Access Read only P0 P31 Output Status 0 The I O line is a pure input 1 The I O line is enabled in output 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 ...

Page 559: ... 0x400E1024 PIOB 0x400E1224 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Input Filter Disable 0 No effect 1 Disables the input glitch filter on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P...

Page 560: ...R Address 0x400E0E30 PIOA 0x400E1030 PIOB 0x400E1230 PIOC Access Write only P0 P31 Set Output Data 0 No effect 1 Sets the data to be driven on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 ...

Page 561: ...1238 PIOC Access Read only or Read write P0 P31 Output Data Status 0 The data to be driven on the I O line is 0 1 The data to be driven on the I O line is 1 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28...

Page 562: ...PIOB 0x400E1240 PIOC Access Write only P0 P31 Input Change Interrupt Enable 0 No effect 1 Enables the Input Change Interrupt on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24...

Page 563: ...0E1248 PIOC Access Read only P0 P31 Input Change Interrupt Mask 0 Input Change Interrupt is disabled on the I O line 1 Input Change Interrupt is enabled on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31...

Page 564: ...IO_MDER Address 0x400E0E50 PIOA 0x400E1050 PIOB 0x400E1250 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Multi Drive Enable 0 No effect 1 Enables Multi Drive on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 ...

Page 565: ...1058 PIOB 0x400E1258 PIOC Access Read only P0 P31 Multi Drive Status 0 The Multi Drive is disabled on the I O line The pin is driven at high and low level 1 The Multi Drive is enabled on the I O line The pin is driven at low level only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 ...

Page 566: ...x400E1064 PIOB 0x400E1264 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Pull Up Enable 0 No effect 1 Enables the pull up resistor on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 ...

Page 567: ...0E1268 PIOC Access Read only P0 P31 Pull Up Status 0 Pull Up resistor is enabled on the I O line 1 Pull Up resistor is disabled on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 ...

Page 568: ...t to 0 in PIO_ABCDSR2 0 Assigns the I O line to the Peripheral A function 1 Assigns the I O line to the Peripheral B function If the same bit is set to 1 in PIO_ABCDSR2 0 Assigns the I O line to the Peripheral C function 1 Assigns the I O line to the Peripheral D function 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 ...

Page 569: ...t to 0 in PIO_ABCDSR1 0 Assigns the I O line to the Peripheral A function 1 Assigns the I O line to the Peripheral C function If the same bit is set to 1 in PIO_ABCDSR1 0 Assigns the I O line to the Peripheral B function 1 Assigns the I O line to the Peripheral D function 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 ...

Page 570: ...x400E0E84 PIOA 0x400E1084 PIOB 0x400E1284 PIOC Access Write only P0 P31 Debouncing Filtering Select 0 No Effect 1 The Debouncing Filter is able to filter pulses with a duration Tdiv_slclk 2 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 ...

Page 571: ...er pulses with a duration Tdiv_slclk 2 29 7 29 PIO Slow Clock Divider Debouncing Register Name PIO_SCDR Address 0x400E0E8C PIOA 0x400E108C PIOB 0x400E128C PIOC Access Read write DIVx Slow Clock Divider Selection for Debouncing Tdiv_slclk 2 DIV 1 Tslow_clock 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 ...

Page 572: ... PIOA 0x400E1094 PIOB 0x400E1294 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Pull Down Enable 0 No effect 1 Enables the pull down resistor on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8...

Page 573: ...only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Pull Down Status 0 Pull Down resistor is enabled on the I O line 1 Pull Down resistor is disabled on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 ...

Page 574: ...A 0x400E10A4 PIOB 0x400E12A4 PIOC Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Output Write Disable 0 No effect 1 Disables writing PIO_ODSR for the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6...

Page 575: ...IOA 0x400E10B0 PIOB 0x400E12B0 PIOC Access Write only P0 P31 Additional Interrupt Modes Enable 0 No effect 1 The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 2...

Page 576: ...IOA 0x400E10B8 PIOB 0x400E12B8 PIOC Access Read only P0 P31 Peripheral CD Status 0 The interrupt source is a Both Edge detection event 1 The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5...

Page 577: ...0C4 PIOB 0x400E12C4 PIOC Access Write only P0 P31 Level Interrupt Selection 0 No effect 1 The interrupt source is a Level detection event 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23...

Page 578: ...10D0 PIOB 0x400E12D0 PIOC Access Write only P0 P31 Falling Edge Low Level Interrupt Selection 0 No effect 1 The interrupt source is set to a Falling Edge detection or Low Level detection event depending on PIO_ELSR 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6...

Page 579: ...Access Read only P0 P31 Edge Level Interrupt Source Selection 0 The interrupt source is a Falling Edge detection if PIO_ELSR 0 or Low Level detection event if PIO_ELSR 1 1 The interrupt source is a Rising Edge detection if PIO_ELSR 0 or High Level detection event if PIO_ELSR 1 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 1...

Page 580: ... 0x400E10E0 PIOB 0x400E12E0 PIOC Access Read only P0 P31 Lock Status 0 The I O line is not locked 1 The I O line is locked 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 ...

Page 581: ...O Input Filter Enable Register on page 559 PIO Input Filter Disable Register on page 559 PIO Multi driver Enable Register on page 564 PIO Multi driver Disable Register on page 565 PIO Pull Up Disable Register on page 566 PIO Pull Up Enable Register on page 566 PIO Peripheral ABCD Select Register 1 on page 568 PIO Peripheral ABCD Select Register 2 on page 569 PIO Output Write Enable Register on pag...

Page 582: ...ct Violation has occurred since the last read of the PIO_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset or code in which a write access has been attempted Note Reading PIO_...

Page 583: ... is enabled 1 Schmitt Trigger is disabled 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 7 6 5 4 3 2 1 0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT...

Page 584: ...CRHR register is a WORD 32 bit ALWYS Parallel Capture Mode Always Sampling 0 The parallel capture mode samples the data when both data enables are active 1 The parallel capture mode samples the data whatever the data enables are HALFS Parallel Capture Mode Half Sampling Independently from the ALWYS bit 0 The parallel capture mode samples all the data 1 The parallel capture mode samples the data on...

Page 585: ...nterrupt Enable 29 7 51 PIO Parallel Capture Interrupt Disable Register Name PIO_PCIDR Address 0x400E0F58 PIOA 0x400E1158 PIOB 0x400E1358 PIOC Access Write only DRDY Parallel Capture Mode Data Ready Interrupt Disable OVRE Parallel Capture Mode Overrun Error Interrupt Disable ENDRX End of Reception Transfer Interrupt Disable RXBUFF Reception Buffer Full Interrupt Disable 31 30 29 28 27 26 25 24 23 ...

Page 586: ...115C PIOB 0x400E135C PIOC Access Read only DRDY Parallel Capture Mode Data Ready Interrupt Mask OVRE Parallel Capture Mode Overrun Error Interrupt Mask ENDRX End of Reception Transfer Interrupt Mask RXBUFF Reception Buffer Full Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBUFF ENDRX OVRE DRDY ...

Page 587: ...run Error 0 No overrun error occurred since the last read of this register 1 At least one overrun error occurred since the last read of this register The OVRE flag is automatically reset when this register is read or when the parallel capture mode is disabled ENDRX End of Reception Transfer 0 The End of Transfer signal from the Reception PDC channel is inactive 1 The End of Transfer signal from th...

Page 588: ...400E0F64 PIOA 0x400E1164 PIOB 0x400E1364 PIOC Access Read only RDATA Parallel Capture Mode Reception Data If DSIZE 0 in PIO_PCMR only the 8 LSBs of RDATA are useful If DSIZE 1 in PIO_PCMR only the 16 LSBs of RDATA are useful 31 30 29 28 27 26 25 24 RDATA 23 22 21 20 19 18 17 16 RDATA 15 14 13 12 11 10 9 8 RDATA 7 6 5 4 3 2 1 0 RDATA ...

Page 589: ...l The SSC s high level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention Featuring connection to two PDC channels the SSC permits interfacing with low processor overhead to the following CODEC s in master or slave mode DAC through dedicated serial interface particularly I2S Magnetic card reader 30 2...

Page 590: ...Block Diagram Figure 30 2 Application Block Diagram SSC Interface PIO PDC APB Bridge MCK System Bus Peripheral Bus TF TK TD RF RK RD Interrupt Control SSC Interrupt PMC Interrupt Management Power Management Test Management SSC Serial AUDIO OS or RTOS Driver Codec Frame Management Line Interface Time Slot Management ...

Page 591: ...6 3 Interrupt The SSC interface has an interrupt line connected to the Nested Vector Interrupt Controller NVIC Handling interrupts requires programming the NVIC before configuring the SSC All SSC interrupts can be enabled disabled configuring the SSC Interrupt mask register Each pending and unmasked SSC interrupt will assert the SSC interrupt line The SSC interrupt ser vice routine can get the int...

Page 592: ...s the SSC to support many slave mode data transfers The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2 Figure 30 3 SSC Functional Block Diagram 30 7 1 Clock Management The transmitter clock can be generated by An external clock received on the TK I O pad The receiver clock The internal clock divider NVIC Frame Sync Controller Clock Output Controller Data Control...

Page 593: ...lue is 4095 in the Clock Mode Register SSC_CMR allowing a Master Clock division by up to 8190 The Divided Clock is provided to both the Receiver and Transmitter When this field is programmed to 0 the Clock Divider is not used and remains inactive When DIV is set to a value equal to or greater than 1 the Divided Clock has a frequency of Mas ter Clock divided by 2 times DIV Each level of the Divided...

Page 594: ...edict able results Figure 30 6 Transmitter Clock Management 30 7 1 3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I O pad The Receive Clock is selected by the CKS field in SSC_RCMR Receive Clock Mode Register Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR The receiver can a...

Page 595: ...wed by synchronization data before data transmission The start event is configured by setting the Transmit Clock Mode Register SSC_TCMR See Start on page 597 The frame synchronization is configured setting the Transmit Frame Mode Register SSC_TFMR See Frame Sync on page 599 To transmit data the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in...

Page 596: ...register depending on the data format selected When the receiver shift register is full the SSC transfers this data in the holding register the sta tus flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register If another transfer occurs before read of the RHR register the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR regis...

Page 597: ...ising edge on TF RF On detection of a low level high level on TF RF On detection of a level change or an edge on TF RF A start can be programmed in the same manner on either side of the Transmit Receive Clock Register RCMR TCMR Thus the start could be on TF Transmit or RF Receive Moreover the Receiver can start when data is detected in the bit stream with the Compare Functions Detection on TF RF i...

Page 598: ... STTDLY STTDLY STTDLY STTDLY Start Falling Edge on TF Start Rising Edge on TF Start Low Level on TF Start High Level on TF Start Any Edge on TF Start Level Change on TF X RK RF Input RD Input RD Input RD Input RD Input RD Input RD Input X BO B1 X BO B1 BO B1 BO B1 BO B1 BO B1 BO B1 B1 BO X X X STTDLY STTDLY STTDLY STTDLY STTDLY STTDLY Start Falling Edge on RF Start Rising Edge on RF Start Low Leve...

Page 599: ...ransfer Transmit Sync Holding Register in the Shifter Register The data length to be sampled shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR SSC_TFMR and has a maximum value of 16 Concerning the Receive Frame Sync Data operation if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception the data sampling ...

Page 600: ...selection is done with the bit STOP in SSC_RCMR 30 7 7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register SSC_TFMR and the Receiver Frame Mode Register SSC_RFMR In either case the user can independently select the event that starts the data transfer START the delay in number of bit periods between the start even...

Page 601: ... 16 Size of Synchro data register SSC_TFMR DATDEF 0 or 1 Data default value ended SSC_TFMR FSDEN Enable send SSC_TSHR SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay Sync Data Default STTDLY Sync Data Ignored RD Default Data DATLEN Data Data Data DATLEN Data Data Default Default Ignored Sync Data Sync Data FSLEN TF RF 1 Start Start From...

Page 602: ... a corresponding bit in interrupt management registers The SSC can be programmed to generate an interrupt when it detects an event The interrupt is controlled by writing SSC_IER Interrupt Enable Register and SSC_IDR Interrupt Disable Reg ister These registers enable and disable respectively the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR Interrupt Mask Register...

Page 603: ... supported by the SSC are not listed here Figure 30 17 Audio Application Block Diagram Figure 30 18 Codec Application Block Diagram SSC RK RF RD TD TF TK Clock SCK Word Select WS Data SD I2S RECEIVER Clock SCK Word Select WS Data SD Right Channel Left Channel MSB MSB LSB SSC RK RF RD TD TF TK Serial Data Clock SCLK Frame sync FSYNC Serial Data Out Serial Data In CODEC Serial Data Clock SCLK Frame ...

Page 604: ...ure 30 19 Time Slot Application Block Diagram SSC RK RF RD TD TF TK SCLK FSYNC Data Out Data in CODEC First Time Slot Serial Data Clock SCLK Frame sync FSYNC Serial Data Out Serial Data in CODEC Second Time Slot First Time Slot Second Time Slot Dstart Dend ...

Page 605: ...o tect Status Register US_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is reset by writing the SSC Write Protect Mode Register SSC_WPMR with the appropriate access key WPKEY The protected registers are SSC Clock Mode Register on page 608 SSC Receive Clock Mode Register on page 609 SSC Receive Frame Mode Register on page 611 SSC Tran...

Page 606: ...g Register SSC_RHR Read only 0x0 0x24 Transmit Holding Register SSC_THR Write only 0x28 Reserved 0x2C Reserved 0x30 Receive Sync Holding Register SSC_RSHR Read only 0x0 0x34 Transmit Sync Holding Register SSC_TSHR Read write 0x0 0x38 Receive Compare 0 Register SSC_RC0R Read write 0x0 0x3C Receive Compare 1 Register SSC_RC1R Read write 0x0 0x40 Status Register SSC_SR Read only 0x000000CC 0x44 Inter...

Page 607: ...eived disables at end of current character reception TXEN Transmit Enable 0 No effect 1 Enables Transmit if TXDIS is not set TXDIS Transmit Disable 0 No effect 1 Disables Transmit If a character is currently being transmitted disables at end of current character transmission SWRST Software Reset 0 No effect 1 Performs a software reset Has priority on any other bit in SSC_CR 31 30 29 28 27 26 25 24...

Page 608: ...n if the WPEN bit is cleared in SSC Write Protect Mode Register DIV Clock Divider 0 The Clock Divider is not active Any Other Value The Divided Clock equals the Master Clock divided by 2 times DIV The maximum bit rate is MCK 2 The minimum bit rate is MCK 2 x 4095 MCK 8190 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DIV 7 6 5 4 3 2 1 0 DIV ...

Page 609: ... shifted out on Receive Clock rising edge 1 The data inputs Data and Frame Sync signals are sampled on Receive Clock rising edge The Frame Sync signal out put is shifted out on Receive Clock falling edge CKI affects only the Receive Clock and not the output clock signal 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDLY 15 14 13 12 11 10 9 8 STOP START 7 6 5 4 3 2 1 0 CKG CKI CKO CKS Va...

Page 610: ... to TAG Receive Sync Data reception PERIOD Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal If 0 no PERIOD signal is generated If not 0 a PERIOD signal is generated each 2 x PERIOD 1 Receive Clock Value Name Description RK Pin 0 NONE None Input only 1 CONTINUOUS Continuous Receive Clock Output 2 TRAN...

Page 611: ... First 0 The lowest significant bit of the data register is sampled first in the bit stream 1 The most significant bit of the data register is sampled first in the bit stream DATNB Data Number per Frame This field defines the number of data words to be received after each transfer start which is equal to DATNB 1 FSLEN Receive Frame Sync Length This field defines the number of bits sampled and stor...

Page 612: ...xtends FSLEN field For details refer to FSLEN bit description on page 611 Value Name Description RF Pin 0 NONE None Input only 1 NEGATIVE Negative Pulse Output 2 POSITIVE Positive Pulse Output 3 LOW Driven Low during data transfer Output 4 HIGH Driven High during data transfer Output 5 TOGGLING Toggling at each start of data transfer Output 6 7 Reserved Undefined Value Name Description 0 POSITIVE ...

Page 613: ...nput is sampled on Transmit clock rising edge 1 The data outputs Data and Frame Sync signals are shifted out on Transmit Clock rising edge The Frame sync signal input is sampled on Transmit clock falling edge CKI affects only the Transmit Clock and not the output clock signal 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDLY 15 14 13 12 11 10 9 8 START 7 6 5 4 3 2 1 0 CKG CKI CKO CKS V...

Page 614: ...Transmit Clock to generate a new Frame Sync Signal If 0 no period signal is generated If not 0 a period signal is generated at each 2 x PERIOD 1 Transmit Clock Value Name Description 0 NONE None 1 CONTINUOUS Transmit Clock enabled only if TF Low 2 TRANSFER Transmit Clock enabled only if TF High Value Name Description 0 CONTINUOUS Continuous as soon as a word is written in the SSC_THR Register if T...

Page 615: ... as multi drive by the PIO Controller the pin is enabled only if the SCC TD output is 1 MSBF Most Significant Bit First 0 The lowest significant bit of the data register is shifted out first in the bit stream 1 The most significant bit of the data register is shifted out first in the bit stream DATNB Data Number per frame This field defines the number of data words to be transferred after each tra...

Page 616: ...on frame sync will generate the interrupt TXSYN Status Register FSLEN_EXT FSLEN Field Extension Extends FSLEN field For details refer to FSLEN bit description on page 615 Value Name Description RF Pin 0 NONE None Input only 1 NEGATIVE Negative Pulse Output 2 POSITIVE Positive Pulse Output 3 LOW Driven Low during data transfer Output 4 HIGH Driven High during data transfer Output 5 TOGGLING Togglin...

Page 617: ... Holding Register Name SSC_RHR Address 0x40004020 Access Read only RDAT Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR 31 30 29 28 27 26 25 24 RDAT 23 22 21 20 19 18 17 16 RDAT 15 14 13 12 11 10 9 8 RDAT 7 6 5 4 3 2 1 0 RDAT ...

Page 618: ...Holding Register Name SSC_THR Address 0x40004024 Access Write only TDAT Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR 31 30 29 28 27 26 25 24 TDAT 23 22 21 20 19 18 17 16 TDAT 15 14 13 12 11 10 9 8 TDAT 7 6 5 4 3 2 1 0 TDAT ...

Page 619: ...eliminary 30 9 9 SSC Receive Synchronization Holding Register Name SSC_RSHR Address 0x40004030 Access Read only RSDAT Receive Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RSDAT 7 6 5 4 3 2 1 0 RSDAT ...

Page 620: ...iminary 30 9 10 SSC Transmit Synchronization Holding Register Name SSC_TSHR Address 0x40004034 Access Read write TSDAT Transmit Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TSDAT 7 6 5 4 3 2 1 0 TSDAT ...

Page 621: ...e 0 Register Name SSC_RC0R Address 0x40004038 Access Read write This register can only be written if the WPEN bit is cleared in SSC Write Protect Mode Register CP0 Receive Compare Data 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CP0 7 6 5 4 3 2 1 0 CP0 ...

Page 622: ...e 1 Register Name SSC_RC1R Address 0x4000403C Access Read write This register can only be written if the WPEN bit is cleared in SSC Write Protect Mode Register CP1 Receive Compare Data 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CP1 7 6 5 4 3 2 1 0 CP1 ...

Page 623: ..._TCR or SSC_TNCR TXBUFE Transmit Buffer Empty 0 SSC_TCR or SSC_TNCR have a value other than 0 1 Both SSC_TCR and SSC_TNCR have a value of 0 RXRDY Receive Ready 0 SSC_RHR is empty 1 Data has been received and loaded in SSC_RHR OVRUN Receive Overrun 0 No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register 1 Data has been loaded in SSC_RHR ...

Page 624: ...ccurred since the last read of the Status Register 1 A compare 1 has occurred since the last read of the Status Register TXSYN Transmit Sync 0 A Tx Sync has not occurred since the last read of the Status Register 1 A Tx Sync has occurred since the last read of the Status Register RXSYN Receive Sync 0 An Rx Sync has not occurred since the last read of the Status Register 1 An Rx Sync has occurred s...

Page 625: ... 1 Enables the End of Transmission Interrupt TXBUFE Transmit Buffer Empty Interrupt Enable 0 No effect 1 Enables the Transmit Buffer Empty Interrupt RXRDY Receive Ready Interrupt Enable 0 No effect 1 Enables the Receive Ready Interrupt OVRUN Receive Overrun Interrupt Enable 0 No effect 1 Enables the Receive Overrun Interrupt ENDRX End of Reception Interrupt Enable 0 No effect 1 Enables the End of ...

Page 626: ...ve Buffer Full Interrupt CP0 Compare 0 Interrupt Enable 0 No effect 1 Enables the Compare 0 Interrupt CP1 Compare 1 Interrupt Enable 0 No effect 1 Enables the Compare 1 Interrupt TXSYN Tx Sync Interrupt Enable 0 No effect 1 Enables the Tx Sync Interrupt RXSYN Rx Sync Interrupt Enable 0 No effect 1 Enables the Rx Sync Interrupt ...

Page 627: ... Disables the End of Transmission Interrupt TXBUFE Transmit Buffer Empty Interrupt Disable 0 No effect 1 Disables the Transmit Buffer Empty Interrupt RXRDY Receive Ready Interrupt Disable 0 No effect 1 Disables the Receive Ready Interrupt OVRUN Receive Overrun Interrupt Disable 0 No effect 1 Disables the Receive Overrun Interrupt ENDRX End of Reception Interrupt Disable 0 No effect 1 Disables the ...

Page 628: ... Buffer Full Interrupt CP0 Compare 0 Interrupt Disable 0 No effect 1 Disables the Compare 0 Interrupt CP1 Compare 1 Interrupt Disable 0 No effect 1 Disables the Compare 1 Interrupt TXSYN Tx Sync Interrupt Enable 0 No effect 1 Disables the Tx Sync Interrupt RXSYN Rx Sync Interrupt Enable 0 No effect 1 Disables the Rx Sync Interrupt ...

Page 629: ...ion Interrupt is enabled TXBUFE Transmit Buffer Empty Interrupt Mask 0 The Transmit Buffer Empty Interrupt is disabled 1 The Transmit Buffer Empty Interrupt is enabled RXRDY Receive Ready Interrupt Mask 0 The Receive Ready Interrupt is disabled 1 The Receive Ready Interrupt is enabled OVRUN Receive Overrun Interrupt Mask 0 The Receive Overrun Interrupt is disabled 1 The Receive Overrun Interrupt i...

Page 630: ...are 0 Interrupt Mask 0 The Compare 0 Interrupt is disabled 1 The Compare 0 Interrupt is enabled CP1 Compare 1 Interrupt Mask 0 The Compare 1 Interrupt is disabled 1 The Compare 1 Interrupt is enabled TXSYN Tx Sync Interrupt Mask 0 The Tx Sync Interrupt is disabled 1 The Tx Sync Interrupt is enabled RXSYN Rx Sync Interrupt Mask 0 The Rx Sync Interrupt is disabled 1 The Rx Sync Interrupt is enabled ...

Page 631: ...k Mode Register on page 608 SSC Receive Clock Mode Register on page 609 SSC Receive Frame Mode Register on page 611 SSC Transmit Clock Mode Register on page 613 SSC Transmit Frame Mode Register on page 615 SSC Receive Compare 0 Register on page 621 SSC Receive Compare 1 Register on page 622 WPKEY Write Protect KEY Should be written at value 0x535343 SSC in ASCII Writing any other value in this fie...

Page 632: ...ccurred since the last read of the SSC_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset or code in which a write access has been attempted Note Reading SSC_WPSR automatically...

Page 633: ...Master Out Slave In MOSI This data line supplies the output data from the master shifted into the input s of the slave s Master In Slave Out MISO This data line supplies the output data from a slave to the input of the master There may be no more than one slave transmitting data during any particular transfer Serial Clock SPCK This control line is driven by the master and regulates the flow of the...

Page 634: ...am Figure 31 2 Application Block Diagram Single Master Multiple Slave Implementation SPI Interface Interrupt Control PIO PDC PMC MCK SPI Interrupt SPCK MISO MOSI NPCS0 NSS NPCS1 NPCS2 NPCS3 APB SPI Master SPCK MISO MOSI NPCS0 NPCS1 NPCS2 SPCK MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 2 NC NPCS3 ...

Page 635: ...Signal Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1 NPCS3 Peripheral Chip Selects Output Unused NPCS0 NSS Peripheral Chip Select Slave Select Output Input ...

Page 636: ...the program mer must first configure the PMC to enable the SPI clock 31 6 3 Interrupt The SPI interface has an interrupt line connected to the Interrupt Controller Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI Table 31 1 I O Lines Instance Signal I O Line Peripheral SPI MISO PA12 A SPI MOSI PA13 A SPI NPCS0 PA11 A SPI NPCS1 PA9 B SPI NPCS1 PA31...

Page 637: ...baud rate generator is activated only in Master Mode 31 7 2 Data Transfer Four combinations of polarity and phase are available for data transfers The clock polarity is programmed with the CPOL bit in the Chip Select Register The clock phase is programmed with the NCPHA bit These two parameters determine the edges of the clock signal on which data is driven and sampled Each of the two parameters h...

Page 638: ...MOSI from master MISO from slave NSS to slave SPCK cycle for reference MSB MSB LSB LSB 6 6 5 5 4 4 3 3 2 2 1 1 Not defined but normally MSB of previous character received 1 2 3 4 5 7 8 6 SPCK CPOL 0 SPCK CPOL 1 1 2 3 4 5 7 MOSI from master MISO from slave NSS to slave SPCK cycle for reference 8 MSB MSB LSB LSB 6 6 5 5 4 4 3 3 1 1 Not defined but normally LSB of previous character transmitted 2 2 6...

Page 639: ...tarts While the data in the Shift Register is shifted on the MOSI line the MISO line is sampled and shifted in the Shift Register Transmission cannot occur without reception Before writing the TDR the PCS field must be set in order to select a slave If new data is written in SPI_TDR during the transfer it stays in it until the current transfer is completed Then the received data is transferred fro...

Page 640: ...r Mode Block Diagram Shift Register SPCK MOSI LSB MSB MISO SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0 3 CPOL NCPHA BITS MCK Baud Rate Generator SPI_CSR0 3 SCBR NPCS3 NPCS0 NPCS2 NPCS1 NPCS0 0 1 PS SPI_MR PCS SPI_TDR PCS MODF Current Peripheral SPI_RDR PCS SPI_CSR0 3 CSAAT PCSDEC MODFDIS MSTR ...

Page 641: ...lizer RDRF 1 TDRE NPCS 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT 0 1 CSAAT 0 TDRE 1 0 PS 0 1 SPI_TDR PCS NPCS no yes SPI_MR PCS NPCS no NPCS 0xF Delay DLYBCS NPCS SPI_TDR PCS NPCS 0xF Delay DLYBCS NPCS SPI_MR PCS SPI_TDR PCS Fixed peripheral Variable peripheral NPCS defines the current Chip Select CSAAT DLYBS DLYBCT refer to the fields of the Chip Select Register correspon...

Page 642: ...XEMPTY End of RX buffer ENDRX End of TX buffer ENDTX RX Buffer Full RXBUFF and TX Buffer Empty TXBUFE status flags behavior within the SPI_SR Status Register during an 8 bit data transfer in fixed mode with the Peripheral Data Controller involved The PDC is programmed to transfer and receive three data The next pointer and counter are not used The RDRF and TDRE are not shown because these flags ar...

Page 643: ...programming 31 7 3 4 Transfer Delays Figure 31 9 shows a chip select transfer change and consecutive transfers on the same chip select Three delays can be programmed to modify the transfer waveforms The delay between chip selects programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register Allows insertion of a delay between release of one chip select and before...

Page 644: ...the SPI_TDR register as the following format xxxxxxx 7 bit LASTXFER 1 bit 1 xxxx 4 bit PCS 4 bit DATA 8 to 16 bit with PCS equals to the chip select to assert as defined in Section 31 8 4 SPI Transmit Data Register and LASTXFER bit at 0 or 1 depending on CSAAT bit Note 1 Optional CSAAT LASTXFER and CSNAAT bits are discussed in Section 31 7 3 9 Peripheral Deselec tion with PDC If LASTXFER is used t...

Page 645: ...Mode PDC Pointer Address Address 4 bytes and PDC Counter Counter 1 for 8 to 16 bit transfer size When using the PDC the TDRE and RDRF flags are handled by the PDC thus the user s application does not have to check those bits Only End of RX Buffer ENDRX End of TX Buffer ENDTX Buffer Full RXBUFF TX Buffer Empty TXBUFE are significant For further details about the Peripheral DMA Controller and user i...

Page 646: ...serted between the two transfers But depending on the application software handling the SPI status register flags by interrupt or polling method or servicing other interrupts or other tasks the processor may not reload the SPI_TDR in time to keep the chip select active low A null Delay Between Consecutive Transfer DLYBCT value in the SPI_CSR register will give even less time for the processor to r...

Page 647: ...t get lost The use of the CSAAT bit might be needed When the CSAAT bit is set at 0 the NPCS does not rise in all cases between two transfers on the same peripheral During a transfer on a Chip Select the flag TDRE rises as soon as the con tent of the SPI_TDR is transferred into the internal shifter When this flag is detected the SPI_TDR can be reloaded If this reload occurs before the end of the cu...

Page 648: ...When a mode fault is detected the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re enabled by writing the SPIEN bit in the SPI_CR Control Register at 1 A NPCS 0 3 Write SPI_TDR TDRE NPCS 0 3 Write SPI_TDR TDRE NPCS 0 3 Write SPI_TDR TDRE DLYBCS PCS A DLYBCS DLYBCT A PCS B B DLYBCS PCS A DLYBCS DLYBCT A PCS B B DLYBCS DLYBCT PCS A A DLYBCS DLYBCT...

Page 649: ...PI_RDR Receive Data Register has not been read before new data is received the Overrun Error bit OVRES in SPI_SR is set As long as this flag is set data is loaded in SPI_RDR The user has to read the status register to clear the OVRES bit When a transfer starts the data shifted out is the data present in the Shift Register If no data has been written in the Transmit Data Register SPI_TDR the last d...

Page 650: ...gister SPI_WPMR If a write access in a write protected register is detected then the WPVS flag in the SPI Write Protection Status Register SPI_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is automatically reset after reading the SPI Write Protection Status Register SPI_WPSR List of the write protected registers Section 31 8 2 SPI Mo...

Page 651: ...4 Interrupt Enable Register SPI_IER Write only 0x18 Interrupt Disable Register SPI_IDR Write only 0x1C Interrupt Mask Register SPI_IMR Read only 0x0 0x20 0x2C Reserved 0x30 Chip Select Register 0 SPI_CSR0 Read write 0x0 0x34 Chip Select Register 1 SPI_CSR1 Read write 0x0 0x38 Chip Select Register 2 SPI_CSR2 Read write 0x0 0x3C Chip Select Register 3 SPI_CSR3 Read write 0x0 0x4C 0xE0 Reserved 0xE4 ...

Page 652: ...er is written the SPI is disabled SWRST SPI Software Reset 0 No effect 1 Reset the SPI A software triggered hardware reset of the SPI interface is performed The SPI is in slave mode after software reset PDC channels are not affected by software reset LASTXFER Last Transfer 0 No effect 1 The current NPCS will be deasserted after the character written in TD has been transferred When CSAAT is set thi...

Page 653: ...Chip Select Registers define the characteristics of the 15 chip selects according to the following rules SPI_CSR0 defines peripheral chip select signals 0 to 3 SPI_CSR1 defines peripheral chip select signals 4 to 7 SPI_CSR2 defines peripheral chip select signals 8 to 11 SPI_CSR3 defines peripheral chip select signals 12 to 14 MODFDIS Mode Fault Detection 0 Mode fault detection is enabled 1 Mode fa...

Page 654: ...PCS xx01 NPCS 3 0 1101 PCS x011 NPCS 3 0 1011 PCS 0111 NPCS 3 0 0111 PCS 1111 forbidden no peripheral is selected x don t care If PCSDEC 1 NPCS 3 0 output signals PCS DLYBCS Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS The DLYBCS time guarantees non over lapping chip selects and solves bus contentions in case of peripherals having lon...

Page 655: ...ed Unused bits read zero PCS Peripheral Chip Select In Master Mode only these bits indicate the value on the NPCS pins at the end of a transfer Otherwise these bits read zero Note When using variable peripheral select mode PS 1 in SPI_MR it is mandatory to also set the WDRBT field to 1 if the SPI_RDR PCS field is to be processed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCS 15 14 13 12 11 10...

Page 656: ...CS 3 0 1110 PCS xx01 NPCS 3 0 1101 PCS x011 NPCS 3 0 1011 PCS 0111 NPCS 3 0 0111 PCS 1111 forbidden no peripheral is selected x don t care If PCSDEC 1 NPCS 3 0 output signals PCS LASTXFER Last Transfer 0 No effect 1 The current NPCS will be deasserted after the character written in TD has been transferred When CSAAT is set this allows to close the communication with the current serial peripheral b...

Page 657: ...d of the SPI_SR OVRES Overrun Error Status 0 No overrun has been detected since the last read of SPI_SR 1 An overrun has occurred since the last read of SPI_SR An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR ENDRX End of RX buffer 0 The Receive Counter Register has not reached 0 since the last write in SPI_RCR 1 or SPI_RNCR 1 1 The Rec...

Page 658: ...ission Registers Empty 0 As soon as data is written in SPI_TDR 1 SPI_TDR and internal shifter are empty If a transfer delay has been defined TXEMPTY is set after the completion of such delay UNDES Underrun Error Status Slave Mode Only 0 No underrun has been detected since the last read of SPI_SR 1 A transfer begins whereas no data has been loaded in the Transmit Data Register SPIENS SPI Enable Sta...

Page 659: ...t Error Interrupt Enable OVRES Overrun Error Interrupt Enable ENDRX End of Receive Buffer Interrupt Enable ENDTX End of Transmit Buffer Interrupt Enable RXBUFF Receive Buffer Full Interrupt Enable TXBUFE Transmit Buffer Empty Interrupt Enable NSSR NSS Rising Interrupt Enable TXEMPTY Transmission Registers Empty Enable UNDES Underrun Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 660: ...rror Interrupt Disable OVRES Overrun Error Interrupt Disable ENDRX End of Receive Buffer Interrupt Disable ENDTX End of Transmit Buffer Interrupt Disable RXBUFF Receive Buffer Full Interrupt Disable TXBUFE Transmit Buffer Empty Interrupt Disable NSSR NSS Rising Interrupt Disable TXEMPTY Transmission Registers Empty Disable UNDES Underrun Error Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 ...

Page 661: ...upt Mask MODF Mode Fault Error Interrupt Mask OVRES Overrun Error Interrupt Mask ENDRX End of Receive Buffer Interrupt Mask ENDTX End of Transmit Buffer Interrupt Mask RXBUFF Receive Buffer Full Interrupt Mask TXBUFE Transmit Buffer Empty Interrupt Mask NSSR NSS Rising Interrupt Mask TXEMPTY Transmission Registers Empty Mask UNDES Underrun Error Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 662: ...K NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured NCPHA is used with CPOL to produce the required clock data relationship between master and slave devices CSNAAT Chip Select Not Active After Transfer Ignored if CSAAT 1 0 The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer ...

Page 663: ...ore performing the first transfer Note If one of the SCBR fields inSPI_CSRx is set to 1 the other SCBR fields in SPI_CSRx must be set to 1 as well if they are required to process transfers If they are not used to transfer data they can be set at any value DLYBS Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition When DLYBS equals zero the NPCS valid to...

Page 664: ...pheral without removing the chip select The delay is always inserted after each transfer and before removing the chip select if needed When DLYBCT equals zero no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers Otherwise the following equation determines the delay Delay Between Consecutive Transfers 32 DLYBCT MCK ...

Page 665: ...rotection is Enabled WPKEY Write Protection Key Password If a value is written in WPEN the value is taken into account only if WPKEY is written with SPI SPI written in ASCII Code ie 0x535049 in hexadecimal List of the write protected registers Section 31 8 2 SPI Mode Register Section 31 8 9 SPI Chip Select Register 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 W...

Page 666: ...R register 1 A Write Protect Violation has occurred since the last read of the SPI_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protection Violation Source This Field indicates the APB Offset of the register concerned by the violation SPI_MR or SPI_CSRx 31 30 29 28 27 26 25 24 23 22 21 2...

Page 667: ... core clock frequencies Below Table 32 1 lists the compatibility level of the Atmel Two wire Interface in Master Mode and a full I2C compatible device Note 1 START b000000001 Ack Sr 32 2 Embedded Characteristics Master Multi Master and Slave Mode Operation Compatibility with Atmel two wire interface serial memory and I2 C compatible devices One two or three bytes for slave address Sequential read ...

Page 668: ...m Figure 32 1 Block Diagram Table 32 2 Abbreviations Abbreviation Description TWI Two wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write APB Bridge PMC MCK Two wire Interface PIO NVIC TWI Interrupt TWCK TWD ...

Page 669: ...Description Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I C RTC I C LCD Controller Slave 1 Slave 2 Slave 3 VDD I C Temp Sensor Slave 4 Rp Pull up value as given by the I C Standard Rp Rp Table 32 3 I O Lines Description Pin Name Pin Description Type TWD Two wire Serial Data Input Output TWCK Two wire Serial Clock Input Output ...

Page 670: ...gram the PIO controller to dedicate TWD and TWCK as peripheral lines The user must not program TWD and TWCK as open drain It is already done by the hardware 32 6 2 Power Management Enable the peripheral clock The TWI interface may be clocked through the Power Management Controller PMC thus the programmer must first configure the PMC to enable the TWI clock 32 6 3 Interrupt The TWI interface has an...

Page 671: ...gure 32 3 A high to low transition on the TWD line while TWCK is high defines the START condition A low to high transition on the TWD line while TWCK is high defines a STOP condition Figure 32 3 START and STOP Conditions Figure 32 4 Transfer Format 32 7 2 Modes of Operation The TWI has six modes of operations Master transmitter mode Master receiver mode Multi master transmitter mode Multi master r...

Page 672: ...ng the slave address indicates the transfer direction 0 in this case MREAD 0 in TWI_MMR The TWI transfers require the slave to acknowledge each received byte During the acknowl edge clock pulse 9th pulse the master releases the data line HIGH enabling the slave to pull it down in order to generate the acknowledge The master polls the data line during this clock pulse and sets the Not Acknowledge b...

Page 673: ...sfer the Serial Clock line is stretched tied low while no new data is written in the TWI_THR or until a STOP command is performed See Figure 32 6 Figure 32 7 and Figure 32 8 Figure 32 6 Master Write with One Data Byte Figure 32 7 Master Write with Multiple Data Bytes TXCOMP TXRDY Write THR DATA STOP Command sent write in TWI_CR TWD A DATA A S DADR W P A DATA n A S DADR W DATA n 1 A P DATA n 2 A TX...

Page 674: ...er data has been received the master sends an acknowledge condition to notify the slave that the data has been received except for the last data after the stop condition See Figure 32 9 When the RXRDY bit is set in the status register a character has been received in the receive holding reg ister TWI_RHR The RXRDY bit is reset when reading the TWI_RHR When a single data byte read is performed with...

Page 675: ... address into the slave device and then switch to Master Receiver mode Note that the second start condition after sending the IADR is sometimes called repeated start Sr in I2C fully compatible devices See Figure 32 12 See Figure 32 11 and Figure 32 13 for Master Write operation with internal address The three internal address bytes are configurable through the Master Mode register TWI_MMR If the s...

Page 676: ...he 10 bit address b2 etc 3 Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 b10 is the LSB of the 10 bit address Figure 32 13 below shows a byte write to an Atmel AT24LC512 EEPROM This demonstrates the use of internal addresses to access the device Figure 32 13 Internal Address Usage S DADR W A IADR 23 16 A IADR 15 8 A IADR 7 0 A DATA A P S DADR W A IADR 15 8 A IADR 7 0 A P DATA A A IADR 7 0 A P DAT...

Page 677: ...setting the PDC TXDIS bit 32 8 7 2 Data Receive with the PDC 1 Initialize the receive PDC memory pointers size 1 etc 2 Configure the master mode DADR CKDIV etc 3 Start the transfer by setting the PDC RXTEN bit 4 Wait for the PDC end RX flag 5 Disable the PDC by setting the PDC RXDIS bit 32 8 8 SMBUS Quick Command Master Mode Only The TWI interface can perform a Quick Command 1 Configure the master...

Page 678: ...he interrupt method requires that the interrupt enable register TWI_IER be configured first Figure 32 15 TWI Write Operation with Single Data Byte without Internal Address Set TWI clock CLDIV CHDIV CKDIV in TWI_CWGR Needed only once Set the Control register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address DADR Transfer direction bit Write bit MREAD 0 Load Transmit ...

Page 679: ...nce Set the Control register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address DADR Internal address size IADRSZ Transfer direction bit Write bit MREAD 0 Load transmit register TWI_THR Data to send Read Status register TXRDY 1 Read Status register TXCOMP 1 Transfer finished Set the internal address TWI_IADR address Yes Yes No No Write STOP command TWI_CR STOP ...

Page 680: ...r Device slave address Internal address size if IADR used Transfer direction bit Write bit MREAD 0 Internal address size 0 Load Transmit register TWI_THR Data to send Read Status register TXRDY 1 Data to send Read Status register TXCOMP 1 END BEGIN Set the internal address TWI_IADR address Yes TWI_THR data to send Yes Yes Yes No No No Write STOP Command TWI_CR STOP Set TWI clock CLDIV CHDIV CKDIV ...

Page 681: ...rol register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address Transfer direction bit Read bit MREAD 1 Start the transfer TWI_CR START STOP Read status register RXRDY 1 Read Status register TXCOMP 1 END BEGIN Yes Yes Set TWI clock CLDIV CHDIV CKDIV in TWI_CWGR Needed only once Read Receive Holding Register No No ...

Page 682: ... SVDIS Set the Master Mode register Device slave address Internal address size IADRSZ Transfer direction bit Read bit MREAD 1 Read Status register TXCOMP 1 END BEGIN Yes Set TWI clock CLDIV CHDIV CKDIV in TWI_CWGR Needed only once Yes Set the internal address TWI_IADR address Start the transfer TWI_CR START STOP Read Status register RXRDY 1 Read Receive Holding register No No ...

Page 683: ...ead but one Read status register TXCOMP 1 END Set the internal address TWI_IADR address Yes Yes Yes No Yes Read Receive Holding register TWI_RHR No Set the Control register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address Internal address size if IADR used Transfer direction bit Read bit MREAD 1 BEGIN Set TWI clock CLDIV CHDIV CKDIV in TWI_CWGR Needed only once No ...

Page 684: ...t reinitiate the data transfer If the user starts a transfer ex DADR START W Write in THR and if the bus is busy the TWI automatically waits for a STOP condition on the bus to initiate the transfer see Figure 32 21 on page 685 Note The state of the bus busy or free is not indicated in the user interface 32 9 2 2 TWI as Master or Slave The automatic reversal from Master to Slave is not supported in...

Page 685: ... the master START sent by the TWI DATA sent by the TWI Bus is busy Bus is free A transfer is programmed DADR W START Write THR Transfer is initiated TWI DATA transfer Transfer is kept Bus is considered as free TWCK Bus is busy Bus is free A transfer is programmed DADR W START Write THR Transfer is initiated TWI DATA transfer Transfer is kept Bus is considered as free Data from a Master Data from T...

Page 686: ...ister RXRDY 0 Read TWI_RHR TXRDY 1 EOSACC 1 Write in TWI_THR Need to perform a master access Program the Master mode DADR SVDIS MSEN CLK R W Read Status Register ARBLST 1 MREAD 1 TXRDY 0 Write in TWI_THR Data to send RXRDY 0 Read TWI_RHR Data to read Read Status Register TXCOMP 0 GENERAL CALL TREATMENT Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Stop Transfer TWI_CR STOP No No No No No...

Page 687: ...ted Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR Slave ADdress field SVACC Slave ACCess flag is set and SVREAD Slave READ indicates the direction of the transfer SVACC remains high until a STOP condition or a repeated START is detected When such a condition is detected EOSACC End Of Slave ACCess flag is set 32 10 4 1 Read S...

Page 688: ...e Figure 32 28 on page 691 and Figure 32 29 on page 692 32 10 4 4 General Call In the case where a GENERAL CALL is performed GACC General Call ACCess flag is set After GACC is set it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence See Figure 32 27 on page 690 32 10 4 5 PDC As it is impossible to know the exact number of data t...

Page 689: ...f a STOP condition or a REPEATED START an address different from SADR is detected SVACC is reset Figure 32 26 on page 689 describes the Write operation Figure 32 26 Write Access Ordered by a Master Notes 1 When SVACC is low the state of SVREAD becomes irrelevant 2 RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read Write THR Read RHR ...

Page 690: ...amming sequence and program a new SADR if the programming sequence matches Figure 32 27 on page 690 describes the General Call access Figure 32 27 Master Performs a General Call Note This method allows the user to create an own programming sequence by choosing the program ming bytes and the number of them The programming sequence has to be provided to the master 0000000 W GENERAL CALL P S A GENERA...

Page 691: ...hronization in Read Mode Notes 1 TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowl edged or non acknowledged 2 At the end of the read sequence TXCOMP is set after a STOP or after a REPEATED_START an address different from SADR 3 SCLWS is automatically set when the clock synchronization mechanism is started DATA1 The clock is stre...

Page 692: ...in Write Mode Notes 1 At the end of the read sequence TXCOMP is set after a STOP or after a REPEATED_START an address different from SADR 2 SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha nism is finished Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD RXRDY SCLWS TXCOMP DATA1 DATA2 SCL is stretched on the last bit of DATA1 As soon as a...

Page 693: ... Figure 32 31 on page 693 describes the repeated start reversal from Write to Read mode Figure 32 31 Repeated Start Reversal from Write to Read Mode Notes 1 In this case if TWI_THR has not been written at the end of the read command the clock is automatically stretched before the ACK 2 TXCOMP is only set at the end of the transmission because after the repeated start SADR is detected again S SADR ...

Page 694: ... used to check the status bits The interrupt method requires that the interrupt enable register TWI_IER be configured first Figure 32 32 Read Write Flowchart in Slave Mode Set the SLAVE mode SADR MSDIS SVEN SVACC 1 TXCOMP 1 GACC 1 Decoding of the programming sequence Prog seq OK Change SADR SVREAD 0 Read Status Register RXRDY 0 Read TWI_RHR TXRDY 1 EOSACC 1 Write in TWI_THR END GENERAL CALL TREATM...

Page 695: ... write 0x00000000 0x0C Internal Address Register TWI_IADR Read write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read write 0x00000000 0x14 0x1C Reserved 0x20 Status Register TWI_SR Read only 0x0000F009 0x24 Interrupt Enable Register TWI_IER Write only N A 0x28 Interrupt Disable Register TWI_IDR Write only N A 0x2C Interrupt Mask Register TWI_IMR Read only 0x00000000 0x30 Receive Ho...

Page 696: ... the START and STOP must both be set In multiple data bytes master read the STOP must be set after the last data received but one In master read mode if a NACK bit is received the STOP is automatically performed In master data write operation a STOP condition will be sent after the transmission of the current data is finished MSEN TWI Master Mode Enabled 0 No effect 1 If MSDIS 0 the master mode is...

Page 697: ... Slave Mode Disabled 0 No effect 1 The slave mode is disabled The shifter and holding characters if it contains data are transmitted in case of read oper ation In write operation the character being transferred must be completely received before disabling QUICK SMBUS Quick Command 0 No effect 1 If Master mode is enabled a SMBUS Quick Command is sent SWRST Software Reset 0 No effect 1 Equivalent to...

Page 698: ...ction 1 Master read direction DADR Device Address The device address is used to access slave devices in read or write mode Those bits are only used in Master mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DADR 15 14 13 12 11 10 9 8 MREAD IADRSZ 7 6 5 4 3 2 1 0 Value Name Description 0 NONE No internal device address 1 1_BYTE One byte internal device address 2 2_BYTE Two byte internal device ...

Page 699: ...eset 0x00000000 SADR Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode SADR must be programmed before enabling the Slave mode or after a general call Writes at other times have no effect 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SADR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 700: ...nternal Address Register Name TWI_IADR Address 0x4001800C 0 0x4001C00C 1 Access Read write Reset 0x00000000 IADR Internal Address 0 1 2 or 3 bytes depending on IADRSZ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IADR 15 14 13 12 11 10 9 8 IADR 7 6 5 4 3 2 1 0 IADR ...

Page 701: ... only used in Master mode CLDIV Clock Low Divider The SCL low period is defined as follows CHDIV Clock High Divider The SCL high period is defined as follows CKDIV Clock Divider The CKDIV is used to increase both SCL high and low periods 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CKDIV 15 14 13 12 11 10 9 8 CHDIV 7 6 5 4 3 2 1 0 CLDIV Tlow CLDIV 2 CKDIV 4 TMCK Thigh CHDIV 2 CKDIV 4 TMCK ...

Page 702: ...reset 0 No character has been received since the last TWI_RHR read operation 1 A byte has been received in the TWI_RHR since the last read RXRDY behavior in Master mode can be seen in Figure 32 10 on page 675 RXRDY behavior in Slave mode can be seen in Figure 32 26 on page 689 Figure 32 29 on page 692 Figure 32 30 on page 693 and Figure 32 31 on page 693 TXRDY Transmit Holding Register Ready autom...

Page 703: ...not addressed SVACC is automatically cleared after a NACK or a STOP condition is detected 1 Indicates that the address decoding sequence has matched A Master has sent SADR SVACC remains high until a NACK or a STOP condition is detected SVACC behavior can be seen in Figure 32 25 on page 689 Figure 32 26 on page 689 Figure 32 30 on page 693 and Fig ure 32 31 on page 693 GACC General Call Access clea...

Page 704: ...Of Slave Access clear on read This bit is only used in Slave mode 0 A slave access is being performing 1 The Slave Access is finished End Of Slave Access is automatically set as soon as SVACC is reset EOSACC behavior can be seen in Figure 32 30 on page 693 and Figure 32 31 on page 693 ENDRX End of RX buffer This bit is only used in Master mode 0 The Receive Counter Register has not reached 0 since...

Page 705: ...e OVRE Overrun Error Interrupt Enable NACK Not Acknowledge Interrupt Enable ARBLST Arbitration Lost Interrupt Enable SCL_WS Clock Wait State Interrupt Enable EOSACC End Of Slave Access Interrupt Enable ENDRX End of Receive Buffer Interrupt Enable ENDTX End of Transmit Buffer Interrupt Enable RXBUFF Receive Buffer Full Interrupt Enable TXBUFE Transmit Buffer Empty Interrupt Enable 0 No effect 1 Ena...

Page 706: ...OVRE Overrun Error Interrupt Disable NACK Not Acknowledge Interrupt Disable ARBLST Arbitration Lost Interrupt Disable SCL_WS Clock Wait State Interrupt Disable EOSACC End Of Slave Access Interrupt Disable ENDRX End of Receive Buffer Interrupt Disable ENDTX End of Transmit Buffer Interrupt Disable RXBUFF Receive Buffer Full Interrupt Disable TXBUFE Transmit Buffer Empty Interrupt Disable 0 No effec...

Page 707: ... Error Interrupt Mask NACK Not Acknowledge Interrupt Mask ARBLST Arbitration Lost Interrupt Mask SCL_WS Clock Wait State Interrupt Mask EOSACC End Of Slave Access Interrupt Mask ENDRX End of Receive Buffer Interrupt Mask ENDTX End of Transmit Buffer Interrupt Mask RXBUFF Receive Buffer Full Interrupt Mask TXBUFE Transmit Buffer Empty Interrupt Mask 0 The corresponding interrupt is disabled 1 The c...

Page 708: ...er or Slave Receive Holding Data 32 11 11 TWI Transmit Holding Register Name TWI_THR Address 0x40018034 0 0x4001C034 1 Access Read write Reset 0x00000000 TXDATA Master or Slave Transmit Holding Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDATA ...

Page 709: ...utions Moreover the association with two peripheral DMA controller PDC channels permits packet handling for these tasks with processor time reduced to a minimum 33 2 Embedded Characteristics Two pin UART Independent receiver and transmitter with a common programmable Baud Rate Generator Even Odd Mark or Space Parity Generation Parity Framing and Overrun Error Detection Automatic Echo Local Loopbac...

Page 710: ...Diagram Peripheral DMA Controller Baud Rate Generator Transmit Receive Interrupt Control Peripheral Bridge Parallel Input Output UTXD URXD Power Management Controller MCK uart_irq APB UART Table 33 1 UART Pin Description Pin Name Description Type URXD UART Receive Data Input UTXD UART Transmit Data Output ...

Page 711: ...only and supports only 8 bit character handling with parity It has no clock pin The UART is made up of a receiver and a transmitter that operate independently and a common baud rate generator Receiver timeout and transmitter time guard are not implemented How ever all the implemented features are compatible with those of a standard USART 33 5 1 Baud Rate Generator The baud rate generator provides ...

Page 712: ... 2 2 Start Detection and Data Sampling The UART only supports asynchronous operations and this affects only its receiver The UART receiver detects the start of a received character by sampling the URXD signal until it detects a valid start bit A low level space on URXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock which is 16 times the baud rate...

Page 713: ...un If UART_RHR has not been read by the software or the Peripheral Data Controller or DMA Controller since the last transfer the RXRDY bit is still set and a new character is received the OVRE status bit in UART_SR is set OVRE is cleared when the software writes the control regis ter UART_CR with the bit RSTSTA Reset Status at 1 Sampling Clock URXD True Start Detection D0 Baud Rate Clock D0 D1 D2 ...

Page 714: ...he reset status command is written the PARE bit remains at 1 Figure 33 7 Parity Error 33 5 2 6 Receiver Framing Error When a start bit is detected it generates a character reception when all the data bits have been sampled The stop bit is also sampled and when it is detected at 0 the FRAME Framing Error bit in UART_SR is set at the same time the RXRDY bit is set The FRAME bit remains high until th...

Page 715: ...ed in the Mode Register and the data stored in the Shift Register One start bit at level 0 then the 8 data bits from the lowest to the highest bit one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure The field PARE in the mode register UART_MR defines whether or not a parity bit is shifted out When a parity bit is enabled it can be selected b...

Page 716: ... three test modes These modes of operation are programmed by using the field CHMODE Channel Mode in the mode register UART_MR The Automatic Echo mode allows bit by bit retransmission When a bit is received on the URXD line it is sent to the UTXD line The transmitter operates normally but has no effect on the UTXD line The Local Loopback mode allows the transmitted characters to be received UTXD an...

Page 717: ...4S Series Preliminary Figure 33 11 Test Modes Receiver Transmitter Disabled RXD TXD Receiver Transmitter Disabled RXD TXD VDD Disabled Receiver Transmitter Disabled RXD TXD Disabled Automatic Echo Local Loopback Remote Loopback VDD ...

Page 718: ... Read write 0x0 0x0008 Interrupt Enable Register UART_IER Write only 0x000C Interrupt Disable Register UART_IDR Write only 0x0010 Interrupt Mask Register UART_IMR Read only 0x0 0x0014 Status Register UART_SR Read only 0x0018 Receive Holding Register UART_RHR Read only 0x0 0x001C Transmit Holding Register UART_THR Write only 0x0020 Baud Rate Generator Register UART_BRGR Read write 0x0 0x0024 0x003C...

Page 719: ...Receiver Disable 0 No effect 1 The receiver is disabled If a character is being processed and RSTRX is not set the character is completed before the receiver is stopped TXEN Transmitter Enable 0 No effect 1 The transmitter is enabled if TXDIS is 0 TXDIS Transmitter Disable 0 No effect 1 The transmitter is disabled If a character is being processed and a character has been written in the UART_THR a...

Page 720: ...Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE PAR 7 6 5 4 3 2 1 0 Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Space parity forced to 0 3 MARK Mark parity forced to 1 4 NO No parity Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC Automatic Echo 2 LOCAL_LOOPBACK Local Loopback 3 REMOTE_LOOPBACK Remote Loopback ...

Page 721: ...rrupt ENDTX Enable End of Transmit Interrupt OVRE Enable Overrun Error Interrupt FRAME Enable Framing Error Interrupt PARE Enable Parity Error Interrupt TXEMPTY Enable TXEMPTY Interrupt TXBUFE Enable Buffer Empty Interrupt RXBUFF Enable Buffer Full Interrupt 0 No effect 1 Enables the corresponding interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXBUFF TXBUFE TXEMPTY...

Page 722: ...upt ENDTX Disable End of Transmit Interrupt OVRE Disable Overrun Error Interrupt FRAME Disable Framing Error Interrupt PARE Disable Parity Error Interrupt TXEMPTY Disable TXEMPTY Interrupt TXBUFE Disable Buffer Empty Interrupt RXBUFF Disable Buffer Full Interrupt 0 No effect 1 Disables the corresponding interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXBUFF TXBUFE T...

Page 723: ...NDTX Mask End of Transmit Interrupt OVRE Mask Overrun Error Interrupt FRAME Mask Framing Error Interrupt PARE Mask Parity Error Interrupt TXEMPTY Mask TXEMPTY Interrupt TXBUFE Mask TXBUFE Interrupt RXBUFF Mask RXBUFF Interrupt 0 The corresponding interrupt is disabled 1 The corresponding interrupt is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXBUFF TXBUFE TXEMPT...

Page 724: ...hannel is inactive 1 The End of Transfer signal from the receiver Peripheral Data Controller channel is active ENDTX End of Transmitter Transfer 0 The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive 1 The End of Transfer signal from the transmitter Peripheral Data Controller channel is active OVRE Overrun Error 0 No overrun error has occurred since the la...

Page 725: ...acters in UART_THR and there are no characters being processed by the transmitter TXBUFE Transmission Buffer Empty 0 The buffer empty signal from the transmitter PDC channel is inactive 1 The buffer empty signal from the transmitter PDC channel is active RXBUFF Receive Buffer Full 0 The buffer full signal from the receiver PDC channel is inactive 1 The buffer full signal from the receiver PDC chan...

Page 726: ...6 7 UART Receiver Holding Register Name UART_RHR Address 0x400E0618 0 0x400E0818 1 Access Read only RXCHR Received Character Last received character if RXRDY is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXCHR ...

Page 727: ... Register Name UART_THR Address 0x400E061C 0 0x400E081C 1 Access Write only TXCHR Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCHR ...

Page 728: ...ART Baud Rate Generator Register Name UART_BRGR Address 0x400E0620 0 0x400E0820 1 Access Read write CD Clock Divisor 0 Baud Rate Clock is disabled 1 to 65 535 MCK CD x 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 7 6 5 4 3 2 1 0 CD ...

Page 729: ...w control by automatic management of the pins RTS and CTS The USART supports the connection to the Peripheral DMA Controller which enables data transfers to the transmitter and from the receiver The PDC provides chained buffer manage ment without any intervention of the processor 34 2 Embedded Characteristics Programmable Baud Rate Generator 5 to 9 bit full duplex synchronous or asynchronous seria...

Page 730: ... Table 34 1 SPI Operating Mode PIN USART SPI Slave SPI Master RXD RXD MOSI MISO TXD TXD MISO MOSI RTS RTS CS CTS CTS CS Peripheral DMA Controller Channel Channel Interrupt Controller Receiver USART Interrupt RXD TXD SCK USART PIO Controller CTS RTS DTR DSR DCD RI Transmitter Modem Signals Control Baud Rate Generator User Interface PMC MCK SLCK DIV MCK DIV APB ...

Page 731: ...2 I O Line Description Name Description Type Active Level SCK Serial Clock I O TXD Transmit Serial Data or Master Out Slave In MOSI in SPI Master Mode or Master In Slave Out MISO in SPI Slave Mode I O RXD Receive Serial Data or Master In Slave Out MISO in SPI Master Mode or Master Out Slave In MOSI in SPI Slave Mode Input RI Ring Indicator Input Low DSR Data Set Ready Input Low DCD Data Carrier De...

Page 732: ...ith all the modem signals On USARTs not equipped with the corresponding pin the associated control bits and statuses have no effect on the behav ior of the USART 34 6 2 Power Management The USART is not continuously clocked The programmer must first enable the USART Clock in the Power Management Controller PMC before using the USART However if the application does not require USART operations the ...

Page 733: ...nal hardware handshaking Optional modem signals management Optional break management Optional multidrop serial communication High speed 5 to 9 bit full duplex synchronous serial communication MSB or LSB first 1 or 2 stop bits Parity even odd marked space or none By 8 or by 16 over sampling frequency Optional hardware handshaking Optional modem signals management Optional break management Optional ...

Page 734: ...high levels of the signal pro vided on the SCK pin must be longer than a Master Clock MCK period The frequency of the signal provided on SCK must be at least 3 times lower than MCK in USART mode or 6 in SPI mode Figure 34 3 Baud Rate Generator 34 7 1 1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode the selected clock is first divided by CD which is field ...

Page 735: ... has a high resolution The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock Table 34 5 Baud Rate Example OVER 0 Source Clock ExpectedBaud Rate Calculation Result CD Actual Baud Rate Error MHz Bit s Bit s 3 686 400 38 400 6 00 6 38 400 00 0 00 4 915 200 38 400 8 00 8 38 400 00 0 00 5 000 000 38 400 8 14 8 39 062 50 1 70 7 372 800 38 400 12 0...

Page 736: ...by the signal on the USART SCK pin No division is active The value written in US_BRGR has no effect The external clock frequency must be at least 3 times lower than the system clock In synchronous mode master USCLKS 0 or 1 CLK0 set to 1 the receive part limits the SCK maximum frequency to MCK 3 in USART mode or MCK 6 in SPI mode When either the external clock SCK or the internal clock divided MCK ...

Page 737: ...FIDI This is performed by the Sampling Divider which performs a division by up to 2047 in ISO7816 Mode The non integer values of the Fi Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value The FI_DI_RATIO field resets to the value 0x174 372 in decimal and is the most common divider between the ISO7816 clock and the bit rat...

Page 738: ...ependently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR If the receiver is disabled during a character reception the USART waits until the end of reception of the current character then the reception is stopped If the transmitter is disabled while it is operating the USART waits the end of transmission of both the current character and character being st...

Page 739: ...re 34 7 Transmitter Status 34 7 3 2 Manchester Encoder When the Manchester encoder is in use characters transmitted through the USART are encoded based on biphase Manchester II format To enable this mode set the MAN field in the US_MR register to 1 Depending on polarity configuration a logic level zero or one is transmit ted as a coded signal one to zero or zero to one Thus a transition always occ...

Page 740: ...one is encoded with a one to zero tran sition If the TX_MPOL field is set to one a logic one is encoded with a one to zero transition and a logic zero is encoded with a zero to one transition Figure 34 9 Preamble Patterns Default Polarity Assumed A start frame delimiter is to be configured using the ONEBIT field in the US_MR register It con sists of a user defined pattern that indicates the beginn...

Page 741: ...ster The USART character for mat is modified and includes sync information Figure 34 10 Start Frame Delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode An hardware recovery system allows a larger clock drift To enable the hardware system the bit in the USART_MAN register must be set If the RXD edge is one 16X clock cycle from the expected edge this is conside...

Page 742: ...t is detected at the fourth sample to 0 Then data bits parity bit and stop bit are sampled on each 8 sampling clock cycle The number of data bits first bit sent and parity mode are selected by the same fields and bits as the transmitter i e respectively CHRL MODE9 MSBF and PAR For the synchronization mechanism only the number of stop bits has no effect on the receiver as it considers only one stop...

Page 743: ...pattern matching is to be defined via the RX_PP field in US_MAN See Figure 34 9 for available preamble patterns Unlike preamble the start frame delimiter is shared between Manchester Encoder and Decoder So if ONEBIT field is set to 1 only a zero encoded Manchester can be detected as a valid start frame delimiter If ONEBIT is set to 0 only a sync pattern is detected as a valid start frame delimiter...

Page 744: ...next valid edge The minimum time threshold to estimate the bit value is three quarters of a bit time If a valid preamble if used followed with a valid start frame delimiter is detected the incoming stream is decoded into NRZ data and passed to USART for processing Figure 34 15 illustrates Manchester pattern mismatch When incoming data stream is passed to the USART the receiver is also able to dete...

Page 745: ...s the decoder is setup to be used in unipolar mode the first bit of the frame has to be a zero to one transition 34 7 3 5 Radio Interface Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Man chester encoded USART These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes The goal ...

Page 746: ...n a logic 1 is sent the modulator out puts an RF signal at frequency F0 and switches to F1 if the data sent is a 0 See Figure 34 19 From the receiver side another carrier frequency is used The RF receiver performs a bit check operation examining demodulated data stream If a valid pattern is detected the receiver switches to receiving mode The demodulated stream is sent to the Manchester decoder Be...

Page 747: ... in synchronous mode Figure 34 20 Synchronous Mode Character Reception 34 7 3 7 Receiver Operations When a character reception is completed it is transferred to the Receive Holding Register US_RHR and the RXRDY bit in the Status Register US_CSR rises If a character is com pleted while the RXRDY is set the OVRE Overrun Error bit is set The last character is transferred into US_RHR and overwrites th...

Page 748: ...if the sampled parity bit does not correspond If the mark parity is used the parity generator of the transmitter drives the parity bit to 1 for all characters The receiver parity checker reports an error if the parity bit is sampled to 0 If the space parity is used the parity generator of the transmitter drives the parity bit to 0 for all characters The receiver parity checker reports an error if ...

Page 749: ... address byte parity bit set when SENDA is written to US_CR In this case the next byte written to US_THR is transmitted as an address Any character written in US_THR without having written the command SENDA is transmitted normally with the parity to 0 34 7 3 10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices The timeguard function enables the transm...

Page 750: ...e receiver waits for a new character is programmed in the TO field of the Receiver Time out Register US_RTOR If the TO field is programmed to 0 the Receiver Time out is disabled and no time out is detected The TIMEOUT bit in US_CSR remains to 0 Otherwise the receiver loads a 16 bit counter with the value pro grammed in TO This counter is decremented at each bit period and reloaded each time a new ...

Page 751: ...ed the counter clock is stopped until a first character is received The idle state on RXD before the start of the frame does not provide a time out This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected If RETTO is performed the counter starts counting down immediately from the value TO This enables generation of a periodic...

Page 752: ... holds the TXD line at least during one character until the user requests the break condition to be removed A break is transmitted by writing the Control Register US_CR with the STTBRK bit to 1 This can be performed at any time either while the transmitter is empty no character in either the Shift Register or in US_THR or when a character is being transmitted If a break is requested while a charac...

Page 753: ...XD line for this period the transmitter resumes normal operations Figure 34 26 illustrates the effect of both the Start Break STTBRK and Stop Break STPBRK commands on the TXD line Figure 34 26 Break Transmission 34 7 3 14 Receive Break The receiver detects a break condition when all data parity and stop bits are low This corre sponds to detecting a framing error with data to 0x00 but FRAME remains...

Page 754: ...if the receiver is disabled and if the status RXBUFF Receive Buffer Full com ing from the PDC channel is high Normally the remote device does not start transmitting while its CTS pin driven by RTS is high As soon as the Receiver is enabled the RTS falls indicating to the remote device that it can start transmitting Defining a new buffer to the PDC clears the status bit RXBUFF and as a result asser...

Page 755: ...fixed The configuration is 8 data bits even parity and 1 or 2 stop bits regardless of the values pro grammed in the CHRL MODE9 PAR and CHMODE fields MSBF can be used to transmit LSB or MSB first Parity Bit PAR can be used to transmit in normal or inverse mode Refer to USART Mode Register on page 774 and PAR Parity Type on page 775 The USART cannot operate concurrently in both receiver and transmit...

Page 756: ...line even if a parity bit is detected Moreover if INACK is set the erroneous received character is stored in the Receive Holding Register as if no error occurred and the RXRDY bit does rise Transmit Character Repetition When the USART is transmitting a character and gets a NACK it can automatically repeat the character before moving on to the next one Repetition is enabled by writing the MAX_ITERA...

Page 757: ...plex point to point wireless communica tion It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers as shown in Figure 34 33 The modulator and demodulator are compliant with the IrDA specification version 1 1 and support data transfer speeds ranging from 2 4 Kb s to 115 2 Kb s The USART IrDA mode is enabled by setting the USART_MODE field in the Mode...

Page 758: ...ximum acceptable error of 1 87 must be met Table 34 12 IrDA Pulse Duration Baud Rate Pulse Duration 3 16 2 4 Kb s 78 13 µs 9 6 Kb s 19 53 µs 19 2 Kb s 9 77 µs 38 4 Kb s 4 88 µs 57 6 Kb s 3 26 µs 115 2 Kb s 1 63 µs Bit Period Bit Period 3 16 Start Bit Data Bits Stop Bit 0 0 0 0 0 1 1 1 1 1 Transmitter Output TXD Table 34 13 IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Ti...

Page 759: ... IrDA Demodulator Operations As the IrDA mode uses the same logic as the ISO7816 note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly 32 768 000 38 400 53 0 63 4 88 40 000 000 38 400 65 0 16 4 88 3 686 400 19 200 12 0 00 9 77 20 000 000 19 200 65 0 16 9 77 32 768 000 19 200 107 0 31 9 77 40 000 000 19 200 130 0 16 ...

Page 760: ...hown in Figure 34 36 Figure 34 36 Typical Connection to a RS485 Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Regis ter US_MR to the value 0x1 The RTS pin is at a level inverse to the TXEMPTY bit Significantly the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character com pletion Figure 34 37 gives an exa...

Page 761: ...its respectively to 1 The disable command forces the corresponding pin to its inactive level i e high The enable command forces the corresponding pin to its active level i e low RTS output pin is automatically controlled in this mode The level changes are detected on the RI DSR DCD and CTS pins If an input change is detected the RIIC DSRIC DCDIC and CTSIC bits in the Channel Status Register US_CSR...

Page 762: ...supplies the output data from the master shifted into the input of the slave Master In Slave Out MISO This data line supplies the output data from a slave to the input of the master Serial Clock SCK This control line is driven by the master and regulates the flow of the data bits The master may transmit data at a variety of baud rates The SCK line cycles once for each bit that is transmitted Slave...

Page 763: ...ternal clock SCK frequency must be at least 6 times lower than the system clock 34 7 8 3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge depending of CPOL and CPHA of the programmed serial clock There is no Start bit no Parity bit and no Stop bit The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register ...

Page 764: ...CPOL 1 MOSI SPI Master TXD SPI Slave RXD NSS SPI Master RTS SPI Slave CTS SCK cycle for reference MSB MSB LSB LSB 6 6 5 5 4 4 3 3 2 2 1 1 1 2 3 4 5 7 8 6 MISO SPI Master RXD SPI Slave TXD SCK CPOL 0 SCK CPOL 1 1 2 3 4 5 7 MOSI SPI Master TXD SPI Slave RXD MISO SPI Master RXD SPI Slave TXD NSS SPI Master RTS SPI Slave CTS SCK cycle for reference 8 MSB MSB LSB LSB 6 6 5 5 4 4 3 3 1 1 2 2 6 ...

Page 765: ...e UNRE bit is cleared by writing the Control Register US_CR with the RSTSTA Reset Status bit to 1 In SPI Master Mode the slave select line NSS is asserted at low level 1 Tbit Time bit before the transmission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit So the slave select line NSS is always released between each character transmission and a minimum delay o...

Page 766: ...or loopback internally or externally 34 7 9 1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin Figure 34 40 Normal Mode Configuration 34 7 9 2 Automatic Echo Mode Automatic echo mode allows bit by bit retransmission When a bit is received on the RXD pin it is sent to the TXD pin as shown in Figure 34 41 Programming the transmitter has no ...

Page 767: ...setting the WPEN bit in the USART Write Protect Mode Register US_WPMR If a write access to the protected registers is detected then the WPVS flag in the USART Write Protect Status Register US_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is automatically reset by reading the USART Write Protect Mode Register US_WPMR with the appropri...

Page 768: ...olding Register US_RHR Read only 0x0 0x001C Transmitter Holding Register US_THR Write only 0x0020 Baud Rate Generator Register US_BRGR Read write 0x0 0x0024 Receiver Time out Register US_RTOR Read write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read write 0x0 0x2C 0x3C Reserved 0x0040 FI DI Ratio Register US_FIDI Read write 0x174 0x0044 Number of Errors Register US_NER Read only 0x0048 Res...

Page 769: ...ect 1 Resets the transmitter RXEN Receiver Enable 0 No effect 1 Enables the receiver if RXDIS is 0 RXDIS Receiver Disable 0 No effect 1 Disables the receiver TXEN Transmitter Enable 0 No effect 1 Enables the transmitter if TXDIS is 0 TXDIS Transmitter Disable 0 No effect 1 Disables the transmitter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTSDIS RTSEN DTRDIS DTREN 15 14 13 12 11 10 9 8 RETTO...

Page 770: ...ing 12 bit periods No effect if no break is being transmitted STTTO Start Time out 0 No effect 1 Starts waiting for a character before clocking the time out counter Resets the status bit TIMEOUT in US_CSR SENDA Send Address 0 No effect 1 In Multidrop Mode only the next character written to the US_THR is sent with the address bit set RSTIT Reset Iterations 0 No effect 1 Resets ITERATION in US_CSR N...

Page 771: ...771 11100B ATARM 31 Jul 12 SAM4S Series Preliminary RTSEN Request to Send Enable 0 No effect 1 Drives the pin RTS to 0 RTSDIS Request to Send Disable 0 No effect 1 Drives the pin RTS to 1 ...

Page 772: ...ct 1 Resets the receiver RSTTX Reset Transmitter 0 No effect 1 Resets the transmitter RXEN Receiver Enable 0 No effect 1 Enables the receiver if RXDIS is 0 RXDIS Receiver Disable 0 No effect 1 Disables the receiver TXEN Transmitter Enable 0 No effect 1 Enables the transmitter if TXDIS is 0 TXDIS Transmitter Disable 0 No effect 1 Disables the transmitter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 773: ... in SPI Master Mode USART_MODE 0xE FCS 0 No effect FCS 1 Forces the Slave Select Line NSS RTS pin to 0 even if USART is no transmitting in order to address SPI slave devices supporting the CSAAT Mode Chip Select Active After Transfer RCS Release SPI Chip Select Applicable if USART operates in SPI Master Mode USART_MODE 0xE RCS 0 No effect RCS 1 Releases the Slave Select Line NSS RTS pin ...

Page 774: ...ONEBIT MODSYNC MAN FILTER MAX_ITERATION 23 22 21 20 19 18 17 16 INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF 15 14 13 12 11 10 9 8 CHMODE NBSTOP PAR SYNC 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE Value Name Description 0x0 NORMAL Normal mode 0x1 RS485 RS485 0x2 HW_HANDSHAKING Hardware Handshaking 0x3 MODEM Modem 0x4 IS07816_T_0 IS07816 Protocol T 0 0x6 IS07816_T_1 IS07816 Protocol T 1 0x8 IRDA ...

Page 775: ...s 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Parity forced to 0 Space 3 MARK Parity forced to 1 Mark 4 NO No parity 6 MULTIDROP Multidrop mode Value Name Description 0 1_BIT 1 stop bit 1 1_5_BIT 1 5 stop bit SYNC 0 or reserved SYNC 1 2 2_BIT 2 stop bits Value Name Description 0 NORMAL Normal Mode 1...

Page 776: ...written in US_THR register or the content read in US_RHR is the same as RXD line Normal mode of operation 1 The data field transmitted on TXD line is inverted voltage polarity only compared to the value written on US_THR regis ter or the content read in US_RHR is inverted compared to what is received on RXD line or ISO7816 IO line Inverted Mode of operation useful for contactless card application ...

Page 777: ...SYNC Manchester Synchronization Mode 0 The Manchester Start bit is a 0 to 1 transition 1 The Manchester Start bit is a 1 to 0 transition ONEBIT Start Frame Delimiter Selector 0 Start Frame delimiter is COMMAND or DATA SYNC 1 Start Frame delimiter is One Bit ...

Page 778: ...eading edge of SPCK and captured on the following edge of SPCK CPHA 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured CPHA is used with CPOL to produce the required clock data relationship between master and slave devices 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 779: ... data relationship between master and slave devices WRDBT Wait Read Data Before Transfer 0 the character transmission starts as soon as a character is written into US_THR register assuming TXRDY was set 1 The character transmission starts when a character is written and only if RXRDY flag is cleared Receiver Holding Reg ister has been read Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC Au...

Page 780: ...pt Enable FRAME Framing Error Interrupt Enable PARE Parity Error Interrupt Enable TIMEOUT Time out Interrupt Enable TXEMPTY TXEMPTY Interrupt Enable ITER Max number of Repetitions Reached Interrupt Enable TXBUFE Buffer Empty Interrupt Enable available in all USART modes of operation RXBUFF Buffer Full Interrupt Enable available in all USART modes of operation NACK Non Acknowledge Interrupt Enable ...

Page 781: ...781 11100B ATARM 31 Jul 12 SAM4S Series Preliminary CTSIC Clear to Send Input Change Interrupt Enable MANE Manchester Error Interrupt Enable 0 No effect 1 Enables the corresponding interrupt ...

Page 782: ...ant only if USART_MODE 0xE or 0xF in USART Mode Register on page 774 RXRDY RXRDY Interrupt Enable TXRDY TXRDY Interrupt Enable OVRE Overrun Error Interrupt Enable TXEMPTY TXEMPTY Interrupt Enable UNRE SPI Underrun Error Interrupt Enable 0 No effect 1 Enables the corresponding interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 UNRE TXEMPTY 7 6 5 4 3 2 1 0 OVRE TXRDY RXR...

Page 783: ... Enable FRAME Framing Error Interrupt Disable PARE Parity Error Interrupt Disable TIMEOUT Time out Interrupt Disable TXEMPTY TXEMPTY Interrupt Disable ITER Max number of Repetitions Reached Interrupt Disable TXBUFE Buffer Empty Interrupt Disable available in all USART modes of operation RXBUFF Buffer Full Interrupt Disable available in all USART modes of operation NACK Non Acknowledge Interrupt Di...

Page 784: ...784 11100B ATARM 31 Jul 12 SAM4S Series Preliminary CTSIC Clear to Send Input Change Interrupt Disable MANE Manchester Error Interrupt Disable 0 No effect 1 Disables the corresponding interrupt ...

Page 785: ... only if USART_MODE 0xE or 0xF in USART Mode Register on page 774 RXRDY RXRDY Interrupt Disable TXRDY TXRDY Interrupt Disable OVRE Overrun Error Interrupt Disable TXEMPTY TXEMPTY Interrupt Disable UNRE SPI Underrun Error Interrupt Disable 0 No effect 1 Disables the corresponding interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 UNRE TXEMPTY 7 6 5 4 3 2 1 0 OVRE TXRDY ...

Page 786: ...terrupt Mask FRAME Framing Error Interrupt Mask PARE Parity Error Interrupt Mask TIMEOUT Time out Interrupt Mask TXEMPTY TXEMPTY Interrupt Mask ITER Max number of Repetitions Reached Interrupt Mask TXBUFE Buffer Empty Interrupt Mask available in all USART modes of operation RXBUFF Buffer Full Interrupt Mask available in all USART modes of operation NACK Non Acknowledge Interrupt Mask RIIC Ring Ind...

Page 787: ... ATARM 31 Jul 12 SAM4S Series Preliminary CTSIC Clear to Send Input Change Interrupt Mask MANE Manchester Error Interrupt Mask 0 The corresponding interrupt is not enabled 1 The corresponding interrupt is enabled ...

Page 788: ...ART_MODE 0xE or 0xF in USART Mode Register on page 774 RXRDY RXRDY Interrupt Mask TXRDY TXRDY Interrupt Mask OVRE Overrun Error Interrupt Mask TXEMPTY TXEMPTY Interrupt Mask UNRE SPI Underrun Error Interrupt Mask 0 The corresponding interrupt is not enabled 1 The corresponding interrupt is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 UNRE TXEMPTY 7 6 5 4 3 2 1 0 OV...

Page 789: ...on as the transmitter is enabled TXRDY becomes 1 1 There is no character in the US_THR RXBRK Break Received End of Break 0 No Break received or End of Break detected since the last RSTSTA 1 Break Received or End of Break detected since the last RSTSTA ENDRX End of Receiver Transfer 0 The End of Transfer signal from the Receive PDC channel is inactive 1 The End of Transfer signal from the Receive P...

Page 790: ...last RSTSTA TXBUFE Transmission Buffer Empty 0 The signal Buffer Empty from the Transmit PDC channel is inactive 1 The signal Buffer Empty from the Transmit PDC channel is active RXBUFF Reception Buffer Full 0 The signal Buffer Full from the Receive PDC channel is inactive 1 The signal Buffer Full from the Receive PDC channel is active NACK Non Acknowledge Interrupt 0 Non Acknowledge has not been ...

Page 791: ...TS pin since the last read of US_CSR RI Image of RI Input 0 RI is set to 0 1 RI is set to 1 DSR Image of DSR Input 0 DSR is set to 0 1 DSR is set to 1 DCD Image of DCD Input 0 DCD is set to 0 1 DCD is set to 1 CTS Image of CTS Input 0 CTS is set to 0 1 CTS is set to 1 MANERR Manchester Error 0 No Manchester error has been detected since the last RSTSTA 1 At least one Manchester error has been dete...

Page 792: ... 0 A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled As soon as the transmitter is enabled TXRDY becomes 1 1 There is no character in the US_THR OVRE Overrun Error 0 No overrun error has occurred since the last RSTSTA 1 At least one overrun error has occurred since the last RSTSTA TXEMPTY Transmitter Empty 0 There are characters in...

Page 793: ...s 0x40024018 0 0x40028018 1 Access Read only RXCHR Received Character Last character received if RXRDY is set RXSYNH Received Sync 0 Last Character received is a Data 1 Last Character received is a Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXSYNH RXCHR 7 6 5 4 3 2 1 0 RXCHR ...

Page 794: ...Next character to be transmitted after the current character if TXRDY is not set TXSYNH Sync Field to be transmitted 0 The next character sent is encoded as a data Start Frame Delimiter is DATA SYNC 1 The next character sent is encoded as a command Start Frame Delimiter is COMMAND SYNC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXSYNH TXCHR 7 6 5 4 3 2 1 0 TXCHR ...

Page 795: ...Clock Divider FP Fractional Part 0 Fractional divider is disabled 1 7 Baudrate resolution defined by FP x 1 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FP 15 14 13 12 11 10 9 8 CD 7 6 5 4 3 2 1 0 CD CD USART_MODE ISO7816 USART_MODE ISO7816 SYNC 0 SYNC 1 or USART_MODE SPI Master or Slave OVER 0 OVER 1 0 Baud Rate Clock Disabled 1 to 65535 Baud Rate Selected Clock 16 CD Baud Rate Selected Cloc...

Page 796: ...Read write This register can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 803 TO Time out Value 0 The Receiver Time out is disabled 1 65535 The Receiver Time out is enabled and the Time out delay is TO x Bit Period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TO 7 6 5 4 3 2 1 0 TO ...

Page 797: ...ead write This register can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 803 TG Timeguard Value 0 The Transmitter Timeguard is disabled 1 255 The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TG ...

Page 798: ...tten if the WPEN bit is cleared in USART Write Protect Mode Register on page 803 FI_DI_RATIO FI Over DI Ratio Value 0 If ISO7816 mode is selected the Baud Rate Generator generates no signal 1 2047 If ISO7816 mode is selected the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FI_DI_RATIO 7 6 5 4 3 2 1 0 FI_DI_RATIO...

Page 799: ...Access Read only This register is relevant only if USART_MODE 0x4 or 0x6 in USART Mode Register on page 774 NB_ERRORS Number of Errors Total number of errors that occurred during an ISO7816 transfer This register automatically clears when read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NB_ERRORS ...

Page 800: ...is register is relevant only if USART_MODE 0x8 in USART Mode Register on page 774 This register can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 803 IRDA_FILTER IrDA Filter Sets the filter of the IrDA demodulator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRDA_FILTER ...

Page 801: ...ition Logic One is coded as a one to zero transition 1 Logic Zero is coded as a one to zero transition Logic One is coded as a zero to one transition RX_PL Receiver Preamble Length 0 The receiver preamble pattern detection is disabled 1 15 The detected preamble length is RX_PL x Bit Period RX_PP Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set 31 30 29 2...

Page 802: ...tion Logic One is coded as a zero to one transition ONE Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register DRIFT Drift compensation 0 The USART can not recover from an important clock drift 1 The USART can recover from clock drift The 16X clock mode must be enabled 01 ALL_ZERO The preamble is composed of 0 s 10 ZERO_ONE The preamble is composed of 01 s 11 ONE_ZERO...

Page 803: ...SART Mode Register on page 774 USART Baud Rate Generator Register on page 795 USART Receiver Time out Register on page 796 USART Transmitter Timeguard Register on page 797 USART FI DI RATIO Register on page 798 USART IrDA FILTER Register on page 800 USART Manchester Configuration Register on page 801 WPKEY Write Protect KEY Should be written at value 0x555341 USA in ASCII Writing any other value i...

Page 804: ...ion has occurred since the last read of the US_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset or code in which a write access has been attempted Note Reading US_WPSR automa...

Page 805: ...adrature signals and connects to the timers counters in order to read the position and speed of the motor through the user interface The Timer Counter block has two global registers which act upon all TC channels The Block Control Register allows the channels to be started simultaneously with the same instruction The Block Mode Register defines the external clock inputs for each channel allowing t...

Page 806: ...rature decoder logic connections are detailed in Figure 35 15 Predefined Connection of the Quadrature Decoder with Timer Counters Timer Counter Channel 0 Timer Counter Channel 1 Timer Counter Channel 2 SYNC Parallel I O Controller TC1XC1S TC0XC0S TC2XC2S INT0 INT1 INT2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA...

Page 807: ...Timer Counter Input Waveform Mode Timer Counter Output TIOB Capture Mode Timer Counter Input Waveform Mode Timer Counter Input Output INT Interrupt Signal Output internal signal SYNC Synchronization Input Signal from configuration register Table 35 3 TC pin list Pin Name Description Type TCLK0 TCLK2 External Clock Input Input TIOA0 TIOA2 I O Line A I O TIOB0 TIOB2 I O Line B I O Table 35 4 I O Lin...

Page 808: ...is incremented at each positive edge of the selected clock When the counter has reached the value 0xFFFF and passes to 0x0000 an overflow occurs and the COVFS bit in TC_SR Status Register is set The current value of the counter is accessible in real time by reading the Counter Value Regis ter TC_CV The counter can be reset by a trigger In this case the counter value passes to 0x0000 on the next va...

Page 809: ...e 35 3 Clock Selection Note In all cases if an external clock is used the duration of each of its levels must be longer than the master clock period The external clock frequency must be at least 2 5 times lower than the mas ter clock Figure 35 2 Clock Chaining Selection Timer Counter Channel 0 SYNC TC0XC0S TIOA0 TIOB0 XC0 XC1 TCLK1 XC2 TCLK2 TCLK0 TIOA1 TIOA2 Timer Counter Channel 1 SYNC TC1XC1S T...

Page 810: ...PCDIS is set to 1 in TC_CMR When disabled the start or the stop actions have no effect only a CLKEN command in the Control Register can re enable the clock When the clock is enabled the CLKSTA bit is set in the Status Register The clock can also be started or stopped a trigger software synchro external or compare always starts the clock The clock can be stopped by an RB load event in Capture Mode ...

Page 811: ... differently from zero just after a trigger especially when a low frequency signal is selected as the clock The following triggers are common to both modes Software Trigger Each channel has a software trigger available by setting SWTRG in TC_CCR SYNC Each channel has a synchronization signal SYNC When asserted this signal has the same effect as a software trigger The SYNC signals of all channels a...

Page 812: ... Mode 35 6 8 Capture Registers A and B Registers A and B RA and RB are used as capture registers This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA The LDRA parameter in TC_CMR defines the TIOA selected edge for the loading of register A and the LDRB parameter defines the TIOA selected edge for the loading of Register B RA is loaded only i...

Page 813: ...n external trig ger The ETRGEDG parameter defines the edge rising falling or both detected to generate an external trigger If ETRGEDG 0 none the external trigger is disabled TIOA RA RB Transfer to System Memory Internal PDC trigger RA RB RA RB T1 T2 T3 T4 System Bus load dependent Tmin 8 MCK T1 T2 T3 T4 ETRGEDG 3 LDRA 3 LDRB 0 ABETRG 0 TIOB TIOA RA Transfer to System Memory Internal PDC trigger RA...

Page 814: ...LKEN CLKDIS BURST TIOB Register C Capture Register A Capture Register B Compare RC Counter ABETRG SWTRG ETRGEDG CPCTRG TC1_IMR Trig LDRBS LDRAS ETRGS TC1_SR LOVRS COVFS SYNC 1 MTIOB TIOA MTIOA LDRA LDBSTOP If RA is not loaded or RB is Loaded If RA is Loaded LDBDIS CPCS INT Edge Detector Edge Detector LDRB Edge Detector CLK OVF RESET Timer Counter Channel MCK Synchronous Edge Detection ...

Page 815: ...e TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event EEVT parameter in TC_CMR Figure 35 6 shows the configuration of the TC channel when programmed in Waveform Operat ing Mode 35 6 11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR Channel Mode Register the behavior of TC_CV varies With any selection RA RB and RC can all be used a...

Page 816: ...e RB Compare RC CPCSTOP Counter EEVT EEVTEDG SYNC SWTRG ENETRG WAVSEL TC1_IMR Trig ACPC ACPA AEEVT ASWTRG BCPC BCPB BEEVT BSWTRG TIOA MTIOA TIOB MTIOB CPAS COVFS ETRGS TC1_SR CPCS CPBS CLK OVF RESET Output Controller Output Controller INT 1 Edge Detector Timer Counter Channel TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 WAVSEL MCK Synchronous Edge Detection ...

Page 817: ...nt trigger or a software trigger can reset the value of TC_CV It is important to note that the trigger may occur at any time See Figure 35 8 RC Compare cannot be programmed to generate a trigger in this configuration At the same time RC Compare can stop the counter clock CPCSTOP 1 in TC_CMR and or disable the counter clock CPCDIS 1 in TC_CMR Figure 35 7 WAVSEL 00 without trigger Time Counter Value...

Page 818: ...note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly See Figure 35 10 In addition RC Compare can stop the counter clock CPCSTOP 1 in TC_CMR and or disable the counter clock CPCDIS 1 in TC_CMR Figure 35 9 WAVSEL 10 Without Trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Example...

Page 819: ...t or a software trigger can modify TC_CV at any time If a trig ger occurs while TC_CV is incrementing TC_CV then decrements If a trigger is received while TC_CV is decrementing TC_CV then increments See Figure 35 12 RC Compare cannot be programmed to generate a trigger in this configuration At the same time RC Compare can stop the counter clock CPCSTOP 1 and or disable the counter clock CPCDIS 1 T...

Page 820: ...igger can modify TC_CV at any time If a trig ger occurs while TC_CV is incrementing TC_CV then decrements If a trigger is received while TC_CV is decrementing TC_CV then increments See Figure 35 14 RC Compare can stop the counter clock CPCSTOP 1 and or disable the counter clock CPCDIS 1 Time Counter Value RC RB RA TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples ...

Page 821: ...14 WAVSEL 11 With Trigger Time Counter Value RC RB RA TIOB TIOA Counter decremented by compare match with RC 0xFFFF Waveform Examples Time Counter Value TIOB TIOA Counter decremented by compare match with RC 0xFFFF Waveform Examples Counter decremented by trigger Counter incremented by trigger RC RB RA ...

Page 822: ...l triggers rising falling or both If EEVTEDG is cleared none no external event is defined If TIOB is defined as an external event signal EEVT 0 TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs In this case the TC channel can only generate a waveform on TIOA When an external event is defined it can be used as a trigger by sett...

Page 823: ...in the corresponding parameter in TC_CMR 35 6 14 Quadrature Decoder Logic 35 6 14 1 Description The quadrature decoder logic is driven by TIOA0 TIOB0 TIOB1 input pins and drives the timer counter of channel 0 and 1 Channel 2 can be used as a time base in case of speed mea surement requirements refer to Figure 35 7 Timer Counter TC User Interface Timer Counter Channel 0 TC_EMR0 TRIGSRCA TIOA0 TIOA0...

Page 824: ... as quadrature decoder is enabled Either speed or position revolution can be measured Position channel 0 accumulates the edges of PHA PHB input signals giving a high accuracy on motor position whereas channel 1 accumu lates the index pulses of the sensor therefore the number of rotations Concatenation of both values provides a high level of precision on motion system position In speed mode positio...

Page 825: ...y means of the MAXFILT field in TC_BMR it is possible to configure a minimum duration for which the pulse is stated as valid When the filter is active pulses with a duration lower than MAXFILT 1 tMCK ns are not passed to down stream logic Filters can be disabled using the FILTER field in the TC_BMR register Timer Counter Channel 0 1 XC0 TIOA TIOB Timer Counter Channel 1 1 XC0 TIOB QDEN Timer Count...

Page 826: ... interfer ence Or simply if vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the beginning of one of the reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic Hall receiver cell of the rotary sensor Any vibration can make the PHA PHB signals toggle for a short duration 1 1 1 MAXFILT PHA PHB IDX TIOA0 TI...

Page 827: ...on PHA PHB motor shaft stopped in such a position that rotary sensor cell is aligned with an edge of the disk rotation PHA PHB PHB Edge area due to system vibration Resulting PHA PHB electrical waveforms PHA Optical Magnetic disk strips stop PHB mechanical shock on system vibration stop PHA PHB electrical waveforms after filtering PHA PHB ...

Page 828: ... edges on a phase signal have sampled the same value on the other phase signal and there is an edge on the other sig nal The 2 consecutive edges of 1 phase signal sampling the same value on other phase signal is not sufficient to declare a direction change for the reason that particulate contamination may mask one or more reflective bar on the optical or magnetic disk of the sensor Refer to Figure...

Page 829: ...rror Detection MAXFILT must be tuned according to several factors such as the system clock frequency MCK type of rotary sensor and rotation speed to be achieved 35 6 14 4 Position and Rotation Measurement When POSEN is set in TC_BMR register position is processed on channel 0 by means of the PHA PHB edge detections and motor revolutions are accumulated in channel 1 timer counter and can be read th...

Page 830: ...ally fed back to TIOA of channel 0 when QDEN and SPEEDEN are set Channel 0 must be configured in capture mode WAVE 0 in TC_CMR0 ABETRG bit field of TC_CMR0 must be configured at 1 to get TIOA as a trigger for this channel EDGTRG can be set to 0x01 to clear the counter on a rising edge of the TIOA signal and LDRA field must be set accordingly to 0x01 to load TC_RA0 at the same time as the counter i...

Page 831: ...g to 0x54494D otherwise the register write will be canceled 35 6 17 Fault Mode At anytime the TC_RCx registers can be used to perform a comparison on the respective cur rent channel counter value TC_CVx with the value of TC_RCx register The CPCSx flags can be set accordingly and an interrupt can be generated This interrupt is processed but requires an unpredictable amount of time to be achieve the...

Page 832: ...0 0x18 Register B TC_RB Read write 2 0 0x00 channel 0x40 0x1C Register C TC_RC Read write 0 0x00 channel 0x40 0x20 Status Register TC_SR Read only 0 0x00 channel 0x40 0x24 Interrupt Enable Register TC_IER Write only 0x00 channel 0x40 0x28 Interrupt Disable Register TC_IDR Write only 0x00 channel 0x40 0x2C Interrupt Mask Register TC_IMR Read only 0 0xC0 Block Control Register TC_BCR Write only 0xC4...

Page 833: ...2 Access Write only CLKEN Counter Clock Enable Command 0 No effect 1 Enables the clock if CLKDIS is not 1 CLKDIS Counter Clock Disable Command 0 No effect 1 Disables the clock SWTRG Software Trigger Command 0 No effect 1 A software trigger is performed the counter is reset and the clock is started 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWTRG CLKDIS CL...

Page 834: ...e of the clock BURST Burst Signal Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG ABETRG ETRGEDG 7 6 5 4 3 2 1 0 LDBDIS LDBSTOP BURST CLKI TCCLKS Value Name Description 0 TIMER_CLOCK1 Clock selected TCLK1 1 TIMER_CLOCK2 Clock selected TCLK2 2 TIMER_CLOCK3 Clock selected TCLK3 3 TIMER_CLOCK4 Clock selected TCLK4 4 TIMER_CLOCK5 Clock selected TCL...

Page 835: ...external trigger CPCTRG RC Compare Trigger Enable 0 RC Compare has no effect on the counter and its clock 1 RC Compare resets the counter and starts the counter clock WAVE Waveform Mode 0 Capture Mode is enabled 1 Capture Mode is disabled Waveform Mode is enabled LDRA RA Loading Edge Selection LDRB RB Loading Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal...

Page 836: ...1 Counter clock is stopped when counter reaches RC 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE WAVSEL ENETRG EEVT EEVTEDG 7 6 5 4 3 2 1 0 CPCDIS CPCSTOP BURST CLKI TCCLKS Value Name Description 0 TIMER_CLOCK1 Clock selected TCLK1 1 TIMER_CLOCK2 Clock selected TCLK2 2 TIMER_CLOCK3 Clock selected TCLK3 3 TIMER_CLOCK4 Clock ...

Page 837: ...er and its clock In this case the selected external event only controls the TIOA output 1 The external event resets the counter and starts the counter clock WAVSEL Waveform Selection WAVE Waveform Mode 0 Waveform Mode is disabled Capture Mode is enabled 1 Waveform Mode is enabled Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge Value Name Description ...

Page 838: ... Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle ...

Page 839: ...xternal Event Effect on TIOB BSWTRG Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle ...

Page 840: ...ead write This register can only be written if the WPEN bit is cleared in TC Write Protect Mode Register on page 858 GCEN Gray Count Enable 0 TIOAx x 0 2 and TIOBx x 0 2 are driven by internal counter of channel x 1 TIOAx x 0 2 and TIOBx x 0 2 are driven by a 2 bit gray counter DOWN DOWN Count 0 Up counter 1 Down counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 841: ...me TC_CVx x 0 2 Address 0x40010010 0 0 0x40010050 0 1 0x40010090 0 2 0x40014010 1 0 0x40014050 1 1 0x40014090 1 2 Access Read only CV Counter Value CV contains the counter value in real time 31 30 29 28 27 26 25 24 CV 23 22 21 20 19 18 17 16 CV 15 14 13 12 11 10 9 8 CV 7 6 5 4 3 2 1 0 CV ...

Page 842: ...egister A value in real time 35 7 7 TC Register B Name TC_RBx x 0 2 Address 0x40010018 0 0 0x40010058 0 1 0x40010098 0 2 0x40014018 1 0 0x40014058 1 1 0x40014098 1 2 Access Read only if WAVE 0 Read write if WAVE 1 This register can only be written if the WPEN bit is cleared in TC Write Protect Mode Register on page 858 RB Register B RB contains the Register B value in real time 31 30 29 28 27 26 2...

Page 843: ...009C 0 2 0x4001401C 1 0 0x4001405C 1 1 0x4001409C 1 2 Access Read write This register can only be written if the WPEN bit is cleared in TC Write Protect Mode Register on page 858 RC Register C RC contains the Register C value in real time 31 30 29 28 27 26 25 24 RC 23 22 21 20 19 18 17 16 RC 15 14 13 12 11 10 9 8 RC 7 6 5 4 3 2 1 0 RC ...

Page 844: ...or WAVE 0 1 RA Compare has occurred since the last read of the Status Register if WAVE 1 CPBS RB Compare Status 0 RB Compare has not occurred since the last read of the Status Register or WAVE 0 1 RB Compare has occurred since the last read of the Status Register if WAVE 1 CPCS RC Compare Status 0 RC Compare has not occurred since the last read of the Status Register 1 RC Compare has occurred sinc...

Page 845: ...s disabled 1 Clock is enabled MTIOA TIOA Mirror 0 TIOA is low If WAVE 0 this means that TIOA pin is low If WAVE 1 this means that TIOA is driven low 1 TIOA is high If WAVE 0 this means that TIOA pin is high If WAVE 1 this means that TIOA is driven high MTIOB TIOB Mirror 0 TIOB is low If WAVE 0 this means that TIOB pin is low If WAVE 1 this means that TIOB is driven low 1 TIOB is high If WAVE 0 thi...

Page 846: ...he Load Overrun Interrupt CPAS RA Compare 0 No effect 1 Enables the RA Compare Interrupt CPBS RB Compare 0 No effect 1 Enables the RB Compare Interrupt CPCS RC Compare 0 No effect 1 Enables the RC Compare Interrupt LDRAS RA Loading 0 No effect 1 Enables the RA Load Interrupt LDRBS RB Loading 0 No effect 1 Enables the RB Load Interrupt ETRGS External Trigger 0 No effect 1 Enables the External Trigg...

Page 847: ...1 Disables the Load Overrun Interrupt if WAVE 0 CPAS RA Compare 0 No effect 1 Disables the RA Compare Interrupt if WAVE 1 CPBS RB Compare 0 No effect 1 Disables the RB Compare Interrupt if WAVE 1 CPCS RC Compare 0 No effect 1 Disables the RC Compare Interrupt LDRAS RA Loading 0 No effect 1 Disables the RA Load Interrupt if WAVE 0 LDRBS RB Loading 0 No effect 1 Disables the RB Load Interrupt if WAV...

Page 848: ...848 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ETRGS External Trigger 0 No effect 1 Disables the External Trigger Interrupt ...

Page 849: ...e Interrupt is disabled 1 The RA Compare Interrupt is enabled CPBS RB Compare 0 The RB Compare Interrupt is disabled 1 The RB Compare Interrupt is enabled CPCS RC Compare 0 The RC Compare Interrupt is disabled 1 The RC Compare Interrupt is enabled LDRAS RA Loading 0 The Load RA Interrupt is disabled 1 The Load RA Interrupt is enabled LDRBS RB Loading 0 The Load RB Interrupt is disabled 1 The Load ...

Page 850: ...Name TC_BCR Address 0x400100C0 0 0x400140C0 1 Access Write only SYNC Synchro Command 0 No effect 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYNC ...

Page 851: ...Quadrature decoding direction change can be disabled using QDTRANS bit 31 30 29 28 27 26 25 24 MAXFILT 23 22 21 20 19 18 17 16 MAXFILT FILTER IDXPHB SWAP 15 14 13 12 11 10 9 8 INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN 7 6 5 4 3 2 1 0 TC2XC2S TC1XC1S TC0XC0S Value Name Description 0 TCLK0 Signal connected to XC0 TCLK0 1 Reserved 2 TIOA1 Signal connected to XC0 TIOA1 3 TIOA2 Signal connecte...

Page 852: ...A 0 PHA TIOA0 is directly driving quadrature decoder logic 1 PHA is inverted before driving quadrature decoder logic INVB INVerted phB 0 PHB TIOB0 is directly driving quadrature decoder logic 1 PHB is inverted before driving quadrature decoder logic SWAP SWAP PHA and PHB 0 No swap between PHA and PHB 1 Swap PHA and PHB internally prior to driving quadrature decoder logic INVIDX INVerted InDeX 0 ID...

Page 853: ...fect 1 Enables the interrupt when a rising edge occurs on IDX input DIRCHG DIRection CHanGe 0 No effect 1 Enables the interrupt when a change on rotation direction is detected QERR Quadrature ERRor 0 No effect 1 Enables the interrupt when a quadrature error occurs on PHA PHB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QERR DIRCHG IDX ...

Page 854: ...ect 1 Disables the interrupt when a rising edge occurs on IDX input DIRCHG DIRection CHanGe 0 No effect 1 Disables the interrupt when a change on rotation direction is detected QERR Quadrature ERRor 0 No effect 1 Disables the interrupt when a quadrature error occurs on PHA PHB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QERR DIRCHG IDX ...

Page 855: ...sabled 1 The interrupt on IDX input is enabled DIRCHG DIRection CHanGe 0 The interrupt on rotation direction change is disabled 1 The interrupt on rotation direction change is enabled QERR Quadrature ERRor 0 The interrupt on quadrature error is disabled 1 The interrupt on quadrature error is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QERR DIRCHG I...

Page 856: ...d of TC_QISR DIRCHG DIRection CHanGe 0 No change on rotation direction since the last read of TC_QISR 1 The rotation direction changed since the last read of TC_QISR QERR Quadrature ERRor 0 No quadrature error since the last read of TC_QISR 1 A quadrature error occurred since the last read of TC_QISR DIR DIRection Returns an image of the actual rotation direction 31 30 29 28 27 26 25 24 23 22 21 2...

Page 857: ...e Register on page 858 ENCF0 ENable Compare Fault Channel 0 0 Disables the FAULT output source CPCS flag from channel 0 1 Enables the FAULT output source CPCS flag from channel 0 ENCF1 ENable Compare Fault Channel 1 0 Disables the FAULT output source CPCS flag from channel 1 1 Enables the FAULT output source CPCS flag from channel 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 858: ...94D TIM in ASCII Protects the registers TC Block Mode Register TC Channel Mode Register Capture Mode TC Channel Mode Register Waveform Mode TC Fault Mode Register TC Stepper Motor Mode Register TC Register A TC Register B TC Register C WPKEY Write Protect KEY Should be written at value 0x54494D TIM in ASCII Writing any other value in this field aborts the write operation of the WPEN bit Always rea...

Page 859: ...performs this selection The SD Memory Card communication is based on a 9 pin interface clock command four data and three power lines and the High Speed MultiMedia Card on a 7 pin interface clock com mand one data three power lines and one reserved for future use The SD Memory Card interface also supports High Speed MultiMedia Card operations The main differences between SD and High Speed MultiMedi...

Page 860: ...ATARM 31 Jul 12 SAM4S Series Preliminary 36 3 Block Diagram Figure 36 1 Block Diagram HSMCI Interface Interrupt Control PIO PDC APB Bridge PMC MCK HSMCI Interrupt MCCK 1 MCCDA 1 MCDA0 1 MCDA1 1 MCDA2 1 MCDA3 1 APB ...

Page 861: ... Input O Output PP Push Pull OD Open Drain 2 3 4 5 6 1 7 MMC 2 3 4 5 6 1 78 SDCard 9 Physical Layer HSMCI Interface Application Layer ex File System Audio Security etc 9 1011 1213 8 Table 36 1 I O Lines Description for 4 bit Configuration Pin Name 1 Pin Description Type 2 Comments MCCDA Command response I O PP OD CMD of an MMC or SDCard SDIO MCCK Clock I O CLK of an MMC or SD Card SDIO MCDA0 MCDA3...

Page 862: ...he programmer must first configure the PMC to enable the HSMCI clock 36 6 3 Interrupt The HSMCI interface has an interrupt line connected to the Nested Vector Interrupt Controller NVIC Handling the HSMCI interrupt requires programming the NVIC before configuring the HSMCI 36 7 Bus Topology Figure 36 3 High Speed MultiMedia Memory Card Bus Topology Table 36 2 I O Lines Instance Signal I O Line Peri...

Page 863: ...roduct MCCK refers to HSMCIx_CK MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy Table 36 4 Bus Topology Pin Number Name Type 1 Description HSMCI Pin Name 2 Slot z 1 DAT 3 I O PP Data MCDz3 2 CMD I O PP OD Command response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT 0 I O PP Data 0 MCDz0 8 DAT 1 I O PP Data 1 MCDz1 9 DAT ...

Page 864: ...bus can be selected in the HSMCI_SDCR register Clearing the SDCBUS bit in this register means that the width is one bit setting it means that the width is four bits In the case of High Speed Multi Media cards only the data line 0 is used The other data lines can be used as independent PIOs Table 36 5 SD Memory Card Bus Signals Pin Number Name Type 1 Description HSMCI Pin Name 2 Slot z 1 CD DAT 3 I...

Page 865: ...me operations have a data token the others transfer their infor mation directly within the command or response structure In this case no data token is present in an operation The bits on the DAT and the CMD lines are transferred synchronous to the clock HSMCI Clock Two types of data transfer commands are defined Sequential commands These commands initiate a continuous data stream They are terminat...

Page 866: ...read in the HSMCI response register HSMCI_RSPR The response size can be from 48 bits up to 136 bits depending on the com mand The HSMCI embeds an error detection to prevent any corrupted data during the transfer The following flowchart shows how to send a command to the card and read the response if needed In this example the status register bits are polled but setting the appropriate bits in the ...

Page 867: ...sponse in the High Speed MultiMe dia Card specification RETURN OK RETURN ERROR 1 RETURN OK Set the command argument HSMCI_ARGR Argument 1 Set the command HSMCI_CMDR Command Read HSMCI_SR CMDRDY Status error flags Read response if required Yes Wait for command ready status flag Check error bits in the status register 1 0 1 Does the command involve a busy indication No Read HSMCI_SR 0 NOTBUSY 1 ...

Page 868: ...efined The card will continuously transfer or program data blocks until a stop transmission command is received Multiple block read or write with pre defined block count since version 3 1 and higher The card will transfer or program the requested number of data blocks and terminate the transaction The stop command is not required at the end of this type of multiple block read or write unless termi...

Page 869: ...block length in bytes HSMCI_MR BlockLenght 16 Number of words to read 0 Poll the bit RXRDY 0 Read data HSMCI_RDR Number of words to read Number of words to read 1 Send READ_SINGLE_BLOCK command 1 Yes Set the PDCMODE bit HSMCI_MR PDCMODE Set the block length in bytes HSMCI_MR BlockLength 16 Configure the PDC channel HSMCI_RPR Data Buffer Address HSMCI_RCR BlockLength 4 HSMCI_PTCR RXTEN Send READ_SI...

Page 870: ...e block size If the bit PDCPADV is 0 then 0x00 value is used when padding data otherwise 0xFF is used If set the bit PDCMODE enables PDC transfer The following flowchart Figure 36 9 shows how to write a single block with or without use of PDC facilities Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register HSMCI_IMR ...

Page 871: ...ckLenght 16 Send WRITE_SINGLE_BLOCK command 1 Set the PDCMODE bit HSMCI_MR PDCMODE Set the block length HSMCI_MR BlockLength 16 Configure the PDC channel HSMCI_TPR Data Buffer Address HSMCI_TCR BlockLength 4 Send WRITE_SINGLE_BLOCK command 1 Read status register HSMCI_SR Poll the bit NOTBUSY 0 Yes RETURN No Yes No Read status register HSMCI_SR Number of words to write 0 Poll the bit TXRDY 0 HSMCI_...

Page 872: ...tional Flow Diagram Note 1 It is assumed that this command has been correctly sent see Figure 36 7 Send SELECT DESELECT_CARD command 1 to select the card Send SET_BLOCKLEN command 1 Set the PDCMODE bit HSMCI_MR PDCMODE Set the block length HSMCI_MR BlockLength 16 Configure the PDC channel HSMCI_TPR Data Buffer Address HSMCI_TCR BlockLength 4 Send WRITE_MULTIPLE_BLOCK command 1 Read status register...

Page 873: ...by default the SD SDIO Card uses only DAT0 for data transfer After initialization the host can change the bus width number of active data lines 36 9 1 SDIO Data Transfer Type SDIO cards may transfer data in either a multi byte 1 to 512 bytes or an optional block format 1 to 511 blocks while the SD memory cards are fixed in the block transfer mode The TRTYP field in the HSMCI Command Register HSMCI...

Page 874: ...T with RW_MULTIPLE_REGISTER CMD60 for 8kB of DATA with nIEN field set to zero to enable the command completion signal in the device 2 Issue RW_MULTIPLE_BLOCK CMD61 to transfer DATA 3 Wait for Completion Signal Received Interrupt 36 10 3 Aborting an ATA Command If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid potential collision on the...

Page 875: ...eration Mode In boot operation mode the processor can read boot data from the slave MMC device by keep ing the CMD line low after power on before issuing CMD1 The data can be read from either the boot area or user area depending on register setting As it is not possible to boot directly on SD CARD a preliminary boot code must be stored in internal Flash 36 11 1 Boot Procedure Processor Mode 1 Conf...

Page 876: ...Write Access During a write access the XFRDONE flag behaves as shown in Figure 36 12 Figure 36 12 XFRDONE During a Write Access CMD line HSMCI read CMD Card response CMDRDY flag Data 1st Block Last Block Not busy flag XFRDONE flag The CMDRDY flag is released 8 tbit after the end of the card response CMD line Card response CMDRDY flag Data bus D0 1st Block Not busy flag XFRDONE flag The CMDRDY flag...

Page 877: ...anywhere in the HSMCI address space from address offset 0x000 to 0x00FC is detected then the WPVS flag in the HSMCI Write Protect Status Register HSMCI_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is reset by writing the HSMCI Write Protect Mode Register HSMCI_WPMR with the appropriate access key WPKEY The protected registers are HS...

Page 878: ...l Timeout Register HSMCI_CSTOR Read write 0x0 0x20 Response Register 1 HSMCI_RSPR Read 0x0 0x24 Response Register 1 HSMCI_RSPR Read 0x0 0x28 Response Register 1 HSMCI_RSPR Read 0x0 0x2C Response Register 1 HSMCI_RSPR Read 0x0 0x30 Receive Data Register HSMCI_RDR Read 0x0 0x34 Transmit Data Register HSMCI_TDR Write 0x38 0x3C Reserved 0x40 Status Register HSMCI_SR Read 0xC0E5 0x44 Interrupt Enable R...

Page 879: ...EN Power Save Mode Enable 0 No effect 1 Enables the Power Saving Mode if PWSDIS is 0 Warning Before enabling this mode the user must set a value different from 0 in the PWSDIV field Mode Register HSMCI_MR PWSDIS Power Save Mode Disable 0 No effect 1 Disables the Power Saving Mode SWRST Software Reset 0 No effect 1 Resets the HSMCI A software triggered hardware reset of the HSMCI interface is perfo...

Page 880: ...d Proof Enable Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full This will guarantee data integrity not bandwidth 0 Disables Read Proof 1 Enables Read Proof WRPROOF Write Proof Enable Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full This will guarantee data integrity not bandwidth 0 Disables Write ...

Page 881: ...ta in write transfer 1 0xFF value is used when padding data in write transfer PADV may be only in manual transfer PDCMODE PDC oriented Mode 0 Disables PDC transfer 1 Enables PDC transfer In this case UNRE and OVRE flags in the MCI Mode Register MCI_SR are deactivated after the PDC transfer has been completed ...

Page 882: ...en two data block trans fers It equals DTOCYC x Multiplier DTOMUL Data Timeout Multiplier Multiplier is defined by DTOMUL as shown in the following table If the data time out set by DTOCYC and DTOMUL has been exceeded the Data Time out Error flag DTOE in the HSMCI Status Register HSMCI_SR rises 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTOMUL DTOCYC Valu...

Page 883: ...tten if the WPEN bit is cleared in HSMCI Write Protect Mode Register on page 903 SDCSEL SDCard SDIO Slot SDCBUS SDCard SDIO Bus Width 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDCBUS SDCSEL Value Name Description 0 SLOTA Slot A is selected 1 SLOTB 2 SLOTC 3 SLOTD Value Name Description 0 1 1 bit 1 Reserved 2 4 4 bit 3 8 8 bit ...

Page 884: ...M4S Series Preliminary 36 14 5 HSMCI Argument Register Name HSMCI_ARGR Address 0x40000010 Access Read write ARG Command Argument 31 30 29 28 27 26 25 24 ARG 23 22 21 20 19 18 17 16 ARG 15 14 13 12 11 10 9 8 ARG 7 6 5 4 3 2 1 0 ARG ...

Page 885: ...T_ACK ATACS IOSPCMD 23 22 21 20 19 18 17 16 TRTYP TRDIR TRCMD 15 14 13 12 11 10 9 8 MAXLAT OPDCMD SPCMD 7 6 5 4 3 2 1 0 RSPTYP CMDNB Value Name Description 0 NORESP No response 1 48_BIT 48 bit response 2 136_BIT 136 bit response 3 R1B R1b response type Value Name Description 0 STD Not a special CMD 1 INIT Initialization CMD 74 clock cycles for initialization sequence 2 SYNC Synchronized CMD Wait f...

Page 886: ...oot Operation Request Start a boot operation mode the host processor can read boot data from the MMC device directly 7 EBO End Boot Operation This command allows the host processor to terminate the boot operation mode Value Name Description 0 NO_DATA No data transfer 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 Reserved Value Name Description 0 SINGLE MMC SDCard Single Block 1...

Page 887: ...knowledge The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued When set to one this field indicates that a Boot acknowledge is expected within a programmable amount of time defined with DTOMUL and DTOCYC fields located in the HSMCI_DTOR register If the acknowledge pattern is not received then an acknowledge timeout error is raised If the acknow...

Page 888: ... Data Block Length This field determines the size of the data block This field is also accessible in the HSMCI Mode Register HSMCI_MR Bits 16 and 17 must be set to 0 if FBYTE is disabled Note In SDIO Byte mode BLKLEN field is not used 31 30 29 28 27 26 25 24 BLKLEN 23 22 21 20 19 18 17 16 BLKLEN 15 14 13 12 11 10 9 8 BCNT 7 6 5 4 3 2 1 0 BCNT Value Name Description 0 MULTIPLE MMC SDCARD Multiple B...

Page 889: ...plier These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer and the assertion of the completion signal The data transfer comprises data phase and the optional busy phase If a non DATA ATA command is issued the HSMCI starts waiting immediately after the end of the response until the comple tion signal Multiplier is defined by CSTO...

Page 890: ...dress 0x40000020 Access Read only RSP Response Note The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses 0x20 to 0x2C N depends on the size of the response 31 30 29 28 27 26 25 24 RSP 23 22 21 20 19 18 17 16 RSP 15 14 13 12 11 10 9 8 RSP 7 6 5 4 3 2 1 0 RSP ...

Page 891: ...y DATA Data to Read 36 14 11 HSMCI Transmit Data Register Name HSMCI_TDR Address 0x40000034 Access Write only DATA Data to Write 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA ...

Page 892: ...Refer to the MMC or SD Specification for more details concerning the CRC Status DTIP Data Transfer in Progress 0 No data transfer in progress 1 The current data transfer is still in progress including CRC16 calculation Cleared at the end of the CRC16 calculation NOTBUSY HSMCI Not Busy This flag must be used only for Write Operations A block write operation uses a simple busy signalling of the writ...

Page 893: ...Counter Register has not reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR 1 The Transmit Counter Register has reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR Note BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the HSMCI Controller SDIOIRQA SDIO Interrupt for Slot A 0 No interr...

Page 894: ... response time out set by MAXLAT in the HSMCI_CMDR has been exceeded Cleared when writing in the HSMCI_CMDR DCRCE Data CRC Error 0 No error 1 A CRC16 error has been detected in the last data block Cleared by reading in the HSMCI_SR register DTOE Data Time out Error 0 No error 1 The data time out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded Cleared by reading in the HSMCI_SR register CS...

Page 895: ... 1 Corrupted Boot Acknowledge signal received OVRE Overrun 0 No error 1 At least one 8 bit received data has been lost not read Cleared when sending a new data transfer command When FERRCTRL in HSMCI_CFG is set to 1 OVRE becomes reset after read UNRE Underrun 0 No error 1 At least one 8 bit data has been sent without valid information not written Cleared when sending a new data transfer command or...

Page 896: ...IRQD SDIO Interrupt for Slot D Interrupt Enable SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable CSRCV Completion Signal Received Interrupt Enable RXBUFF Receive Buffer Full Interrupt Enable TXBUFE Transmit Buffer Empty Interrupt Enable RINDE Response Index Error Interrupt Enable RDIRE Response Direction Error Interrupt Enable RCRCE Response CRC Error Interrupt Enable RENDE Response End B...

Page 897: ... CSTOE Completion Signal Timeout Error Interrupt Enable FIFOEMPTY FIFO empty Interrupt enable XFRDONE Transfer Done Interrupt enable ACKRCV Boot Acknowledge Interrupt Enable ACKRCVE Boot Acknowledge Error Interrupt Enable OVRE Overrun Interrupt Enable UNRE Underrun Interrupt Enable 0 No effect 1 Enables the corresponding interrupt ...

Page 898: ...le SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable CSRCV Completion Signal received interrupt Disable RXBUFF Receive Buffer Full Interrupt Disable TXBUFE Transmit Buffer Empty Interrupt Disable RINDE Response Index Error Interrupt Disable RDIRE Response Direction Error Interrupt Disable RCRCE Response CRC Error Interrupt Disable RENDE Response End Bit Error Interrupt Disable RTOE Respon...

Page 899: ...l Time out Error Interrupt Disable FIFOEMPTY FIFO empty Interrupt Disable XFRDONE Transfer Done Interrupt Disable ACKRCV Boot Acknowledge Interrupt Disable ACKRCVE Boot Acknowledge Error Interrupt Disable OVRE Overrun Interrupt Disable UNRE Underrun Interrupt Disable 0 No effect 1 Disables the corresponding interrupt ...

Page 900: ...sk SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask CSRCV Completion Signal Received Interrupt Mask RXBUFF Receive Buffer Full Interrupt Mask TXBUFE Transmit Buffer Empty Interrupt Mask RINDE Response Index Error Interrupt Mask RDIRE Response Direction Error Interrupt Mask RCRCE Response CRC Error Interrupt Mask RENDE Response End Bit Error Interrupt Mask RTOE Response Time out Error Interr...

Page 901: ...upt Mask FIFOEMPTY FIFO Empty Interrupt Mask XFRDONE Transfer Done Interrupt Mask ACKRCV Boot Operation Acknowledge Received Interrupt Mask ACKRCVE Boot Operation Acknowledge Error Interrupt Mask OVRE Overrun Interrupt Mask UNRE Underrun Interrupt Mask 0 The corresponding interrupt is not enabled 1 The corresponding interrupt is enabled ...

Page 902: ...amount of data is written in the internal FIFO 1 A write transfer starts as soon as one data is written into the FIFO FERRCTRL Flow Error flag reset control mode 0 When an underflow overflow condition flag is set a new Write Read command is needed to reset the flag 1 When an underflow overflow condition flag is set a read status resets the flag HSMODE High Speed Mode 0 Default bus timing mode 1 If...

Page 903: ...f WP_KEY corresponds to 0x4D4349 MCI in ASCII WP_KEY Write Protection Key password Should be written at value 0x4D4349 ASCII code for MCI Writing any other value in this field has no effect Protects the registers HSMCI Mode Register HSMCI Data Timeout Register HSMCI SDCard SDIO Register HSMCI Completion Signal Timeout Register HSMCI Configuration Register 31 30 29 28 27 26 25 24 WP_KEY 0x4D M 23 2...

Page 904: ... attempted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WP_VSRC 15 14 13 12 11 10 9 8 WP_VSRC 7 6 5 4 3 2 1 0 WP_VS Value Name Description 0 NONE No Write Protection Violation occurred since the last read of this register WP_SR 1 WRITE Write Protection detected unauthorized attempt to write a control register had occurred since the last read 2 RESET Software reset had been performed while Write...

Page 905: ...apable of comparing a pro grammed value to the counter of the synchronous channels counter of channel 0 These comparisons are intended to generate software interrupts to trigger pulses on the 2 indepen dent event lines in order to synchronize ADC conversions with a lot of flexibility independently of the PWM outputs and to trigger PDC transfer requests The PWM outputs can be overridden synchronous...

Page 906: ...providing an asynchronous protection of outputs Stepper motor control 2 Channels 37 3 Block Diagram Figure 37 1 Pulse Width Modulation Controller Block Diagram APB ADC Comparison Units Interrupt Controller Interrupt Generator event line 0 event line 1 Events Generator event line x Comparator Clock Selector Counter Channel 0 Duty Cycle Period Update APB Interface CLOCK Generator PIO PMC Dead Time G...

Page 907: ... or may not be enabled If an application requires only four channels then only four PIO lines will be assigned to PWM outputs Table 37 1 I O Line Description Name Description Type PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output PWMFIx PWM Fault Input x Input Table 37 2 I O Lines Instance Signal I O Line Peripheral PWM PWMFI0 PA9 C PWM PWMH0 PA...

Page 908: ...troller Using the PWM interrupt requires the Interrupt Controller to be programmed first Note that it is not recommended to use the PWM interrupt line in edge sensitive mode 37 5 4 Fault Inputs The PWM has the FAULT inputs connected to the different modules Please refer to the imple mentation of these module within the product for detailed information about the fault generation procedure The PWM r...

Page 909: ...or module provides 13 clocks Each channel can independently choose one of the clock generator outputs Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers Table 37 4 Fault Inputs Fault Inputs External PWM Fault Input Number Polarity Level 1 Fault Input ID PA9 PWMFI0 User Defined 0 Main OSC 1 1 ADC 1 2 Anal...

Page 910: ...K 256 FMCK 512 FMCK 1024 two linear dividers 1 1 2 1 3 1 255 that provide two separate clocks clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter The selection of the clock to be divided is made according to the PREA PREB field of the PWM Clock register PWM_CLK The resulting clock clkA clkB is the clock selected divided by DIVA DIVB field value Afte...

Page 911: ...decremented according to the channel configuration and comparators matches The size of the counter is 16 bits A comparator used to compute the OCx output waveform according to the counter value and the configuration The counter value can be the one of the channel counter or the one of the channel 0 counter according to SYNCx bit in the PWM Sync Channels Mode Register on page 942 PWM_SCM A 2 bit co...

Page 912: ...d in the CPRE field of the PWM Channel Mode Register on page 970 PWM_CMRx This field is reset at 0 the waveform period This channel parameter is defined in the CPRD field of the PWM_CPRDx register If the waveform is left aligned then the output waveform period depends on the counter source clock and can be calculated By using the PWM master clock MCK divided by an X given prescaler value with X be...

Page 913: ...t This ends the period Thus for the same CPRD value the period for a center aligned channel is twice the period for a left aligned channel Waveforms are fixed at 0 when CDTY CPRD and CPOL 0 CDTY 0 and CPOL 1 Waveforms are fixed at 1 once the channel is enabled when CDTY 0 and CPOL 0 CDTY CPRD and CPOL 1 The waveform polarity must be set before enabling the channel This immediately affects the chan...

Page 914: ...re 37 5 Waveform Properties Channel x slected clock CHIDx PWM_SR Center Aligned CPRD PWM_CPRDx CDTY PWM_CDTYx PWM_CCNTx Output Waveform OCx CPOL PWM_CMRx 0 Output Waveform OCx CPOL PWM_CMRx 1 Counter Event CHIDx PWM_ISR CES PWM_CMRx 0 Left Aligned CPRD PWM_CPRDx CDTY PWM_CDTYx PWM_CCNTx Output Waveform OCx CPOL PWM_CMRx 0 Output Waveform OCx CPOL PWM_CMRx 1 CALG PWM_CMRx 0 CALG PWM_CMRx 1 Period P...

Page 915: ...ad times also called dead bands or non overlapping times are inserted between the edges of the two complementary outputs DTOHx and DTOLx Note that enabling or disabling the dead time generator is allowed only if the chan nel is disabled The dead time is adjustable by the PWM Channel Dead Time Register PWM_DTx Both out puts of the dead time generator can be adjusted separately by DTH and DTL The de...

Page 916: ... Selection Set Register and PWM Output Selection Set Update Register PWM_OSS and PWM_OSSUPD enable the override of the outputs of a channel regardless of other channels In the same way the clear registers PWM Output Selection Clear Register and PWM Output Selection Clear Update Register PWM_OSC and PWM_OSCUPD disable the override of the outputs of a channel regardless of other channels DTHx DTLx o...

Page 917: ...peripheral does not have Fault Clear man agement then the FMOD configuration to use must be FMOD 1 to avoid spurious fault detection Check the corresponding peripheral documentation for details on handling fault generation The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR regis ter When the filter is activated glitches on fault inputs with a width inferior...

Page 918: ...chanism resets the counter of this channel and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the PWM Fault Protection Value Register PWM_FPV The output forcing is made asynchronously to the channel counter CAUTION To prevent an unexpected activation of the status flag FSy in the PWM_FSR register the FMODy bit can be set to 1 only if the FPOLy bit has been previo...

Page 919: ...ent from channel 0 can be enabled or disabled inde pendently from others by the CHIDx bit in PWM_ENA and PWM_DIS registers Defining a channel as a synchronous channel while it is an asynchronous channel by writing the bit SYNCx to 1 while it was at 0 is allowed only if the channel is disabled at this time CHIDx 0 in PWM_SR register In the same way defining a channel as an asynchronous channel whil...

Page 920: ...Control Register PWM_SCUC which allows to update synchronously at the same PWM period the synchronous channels If the bit UPDULOCK is set to 1 the update is done at the next PWM period of the synchronous channels If the UPDULOCK bit is not set to 1 the update is locked and cannot be performed After writing the UPDULOCK bit to 1 it is held at this value until the update occurs then it is read 0 Tab...

Page 921: ...alue must be done by writing in their respective update registers with the CPU respectively PWM_CPRDUPDx PWM_CDTYUPDx PWM_DTUPDx and PWM_SCUPUPD To trigger the update of the period value and the dead time values the user must use the bit UPDULOCK of the PWM Sync Channels Update Control Register PWM_SCUC which allows to update synchronously at the same PWM period the synchronous channels If the bit...

Page 922: ...HID0 in the PWM_ENA register 5 If an update of the period value and or of the dead time values is required write regis ters that need to be updated PWM_CPRDUPDx PWM_DTUPDx else go to Step 8 6 Set UPDULOCK to 1 in PWM_SCUC 7 The update of these registers will occur at the beginning of the next PWM period At this moment the bit UPDULOCK is reset go to Step 5 for new values 8 If an update of the duty...

Page 923: ...utomatically the duty values and the update period value Using the PDC removes processor overhead by reducing its intervention during the transfer This significantly reduces the number of clock cycles required for a data transfer which improves microcontroller performance The PDC must write the duty cycle values in the synchronous channels index order For exam ple if the channels 0 1 and 3 are syn...

Page 924: ... PWM_CPRDUPDx PWM_DTUPDx else go to Step 10 8 Set UPDULOCK to 1 in PWM_SCUC 9 The update of these registers will occur at the beginning of the next PWM period At this moment the bit UPDULOCK is reset go to Step 7 for new values 10 If an update of the update period value is required check first that write of a new update value is possible by polling the flag WRDY or by waiting for the corresponding...

Page 925: ...nize ADC see Section 37 6 4 PWM Event Lines to generate software interrupts and to trigger PDC transfer requests for the synchronous channels see Method 3 Automatic write of duty cycle values and automatic trigger of the update on page 923 Figure 37 14 Comparison Unit Block Diagram CCNT0 CDTYUPD 0x20 0x40 0x60 UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1 CDTY UPRUPD 0x1 0x3 CMP0 match transfer request WRDY 0x0 ...

Page 926: ...tion can be modified while the channel 0 is enabled by using the PWM Comparison x Mode Update Register PWM_CMPMUPDx registers for the comparison x In the same way the comparison x value can be modified while the channel 0 is enabled by using the PWM Comparison x Value Update Register PWM_CMPVUPDx registers for the comparison x The update of the comparison x configuration and the comparison x value...

Page 927: ...on an event line when at least one of the selected comparisons is matching The comparisons can be selected or unselected inde pendently by the CSEL bits in the PWM Event Line x Register PWM_ELMRx for the Event Line x CCNT0 CVUPD 0x6 0x2 CVMVUPD CV 0x6 0x2 0x6 0x6 CVM Comparison Update CMPU CTRUPD 0x1 0x2 CPR 0x1 0x3 0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 CPRCNT 0x0 0x1 0x2 0x3 0x0 0x1 0x2...

Page 928: ... use PWM_CPRDUPDx register to update PWM_CPRDx as explained below Configuration of the duty cycle for each channel CDTY in the PWM_CDTYx register Writing in PWM_CDTYx register is possible while the channel is disabled After validation of the channel the user must use PWM_CDTYUPDx register to update PWM_CDTYx as explained below Configuration of the dead time generator for each channel DTH and DTL i...

Page 929: ...M Channel Period Update Register and the PWM Channel Dead Time Update Register PWM_CDTYUPDx PWM_CPRDUPDx and PWM_DTUPDx to change waveform parameters while the channel is still enabled If the channel is an asynchronous channel SYNCx 0 in PWM Sync Channels Mode Register PWM_SCM these registers hold the new period duty cycle and dead times values until the end of the current PWM period and update th...

Page 930: ...the end of the update period of synchronous channels when UPRCNT is equal to UPR in PWM Sync Channels Update Period Register PWM_SCUP and the end of the cur rent PWM period then updates the value for the next period Note If the update register PWM_SCUPUPD is written several times between two updates only the last written value is taken into account Note Changing the update period does make sense o...

Page 931: ...ge respectively the comparison values and the comparison configurations while the channel 0 is still enabled These registers hold the new values until the end of the comparison update period when CUPRCNT is equal to CUPR in PWM Comparison x Mode Register PWM_CMPMx and the end of the current PWM period then update the val ues for the next period CAUTION to be taken into account the write of the reg...

Page 932: ... UNRE or CMPMx or CMPUx the interrupt remains active until a read operation in the PWM_ISR2 register occurs A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and PWM_IER2 registers A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR1 and PWM_IDR2 registers 37 6 5 7 Write Protect Registers To prevent any single software error that may corrup...

Page 933: ...p by means of the WPCMD and WPRG fields in PWM_WPCR register If at least one Write Protect is active the register group is write protected The field WPCMD allows to perform the following actions depending on its value 0 Disabling the Write Protect SW of the register groups of which the bit WPRG is at 1 1 Enabling the Write Protect SW of the register groups of which the bit WPRG is at 1 2 Enabling ...

Page 934: ... Enable Register 2 PWM_IER2 Write only 0x38 PWM Interrupt Disable Register 2 PWM_IDR2 Write only 0x3C PWM Interrupt Mask Register 2 PWM_IMR2 Read only 0x0 0x40 PWM Interrupt Status Register 2 PWM_ISR2 Read only 0x0 0x44 PWM Output Override Value Register PWM_OOV Read write 0x0 0x48 PWM Output Selection Register PWM_OS Read write 0x0 0x4C PWM Output Selection Set Register PWM_OSS Write only 0x50 PW...

Page 935: ...ode Update Register PWM_CMPMUPD2 Write only 0x160 PWM Comparison 3 Value Register PWM_CMPV3 Read write 0x0 0x164 PWM Comparison 3 Value Update Register PWM_CMPVUPD3 Write only 0x168 PWM Comparison 3 Mode Register PWM_CMPM3 Read write 0x0 0x16C PWM Comparison 3 Mode Update Register PWM_CMPMUPD3 Write only 0x170 PWM Comparison 4 Value Register PWM_CMPV4 Read write 0x0 0x174 PWM Comparison 4 Value Up...

Page 936: ...num 0x20 0x04 PWM Channel Duty Cycle Register 1 PWM_CDTY Read write 0x0 0x200 ch_num 0x20 0x08 PWM Channel Duty Cycle Update Register 1 PWM_CDTYUPD Write only 0x200 ch_num 0x20 0x0C PWM Channel Period Register 1 PWM_CPRD Read write 0x0 0x200 ch_num 0x20 0x10 PWM Channel Period Update Register 1 PWM_CPRDUPD Write only 0x200 ch_num 0x20 0x14 PWM Channel Counter Register 1 PWM_CCNT Read only 0x0 0x20...

Page 937: ...e Clock Selection 31 30 29 28 27 26 25 24 PREB 23 22 21 20 19 18 17 16 DIVB 15 14 13 12 11 10 9 8 PREA 7 6 5 4 3 2 1 0 DIVA DIVA DIVB CLKA CLKB 0 CLKA CLKB clock is turned off 1 CLKA CLKB clock is clock selected by PREA PREB 2 255 CLKA CLKB clock is clock selected by PREA PREB divided by DIVA DIVB factor PREA PREB Divider Input Clock 0 0 0 0 MCK 0 0 0 1 MCK 2 0 0 1 0 MCK 4 0 0 1 1 MCK 8 0 1 0 0 MC...

Page 938: ...ss 0x40020008 Access Write only This register can only be written if the bits WPSWS1 and WPHWS1 are cleared in PWM Write Protect Status Register on page 965 CHIDx Channel ID 0 No effect 1 Disable PWM output for channel x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHID3 CHID2 CHID1 CHID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 939: ...terrupt Enable Register 1 Name PWM_IER1 Address 0x40020010 Access Write only CHIDx Counter Event on Channel x Interrupt Enable FCHIDx Fault Protection Trigger on Channel x Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHID3 CHID2 CHID1 CHID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FCHID3 FCHID2 FCHID1 FCHID0 15 14 13 12 11 10 9 8 7 6...

Page 940: ... PWM Interrupt Mask Register 1 Name PWM_IMR1 Address 0x40020018 Access Read only CHIDx Counter Event on Channel x Interrupt Mask FCHIDx Fault Protection Trigger on Channel x Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FCHID3 FCHID2 FCHID1 FCHID0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHID3 CHID2 CHID1 CHID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FCHID3 FCHID2 FCHID1 FCHI...

Page 941: ... has occurred since the last read of the PWM_ISR1 register FCHIDx Fault Protection Trigger on Channel x 0 No new trigger of the fault protection since the last read of the PWM_ISR1 register 1 At least one trigger of the fault protection since the last read of the PWM_ISR1 register Note Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FCHI...

Page 942: ...NC1 SYNC0 Value Name Description 0 MODE0 Manual write of double buffer registers and manual update of synchronous channels 1 1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 2 2 MODE2 Automatic write of duty cycle update registers by the PDC and automatic update of synchronous channels 2 3 Reserved UPDM PTRM WRDY Flag and PDC Transfer Request 0 x The WRD...

Page 943: ...f the UPDM field is set to 0 in PWM Sync Channels Mode Register on page 942 writing the UPDULOCK bit to 1 triggers the update of the period value the duty cycle and the dead time values of synchronous channels at the beginning of the next PWM period If the field UPDM is set to 1 or 2 writing the UPDULOCK bit to 1 triggers only the update of the period value and of the dead time values of synchrono...

Page 944: ...een each update of the synchronous channels if automatic trigger of the update is activated UPDM 1 or UPDM 2 in PWM Sync Channels Mode Register on page 942 This time is equal to UPR 1 periods of the synchronous channels UPRCNT Update Period Counter Reports the value of the Update Period Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPRCNT UPR ...

Page 945: ...unexpected automatic trigger of the update of syn chronous channels UPRUPD Update Period Update Defines the wanted time between each update of the synchronous channels if automatic trigger of the update is activated UPDM 1 or UPDM 2 in PWM Sync Channels Mode Register on page 942 This time is equal to UPR 1 periods of the synchronous channels 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 946: ... TX Buffer Interrupt Enable TXBUFE PDC TX Buffer Empty Interrupt Enable UNRE Synchronous Channels Update Underrun Error Interrupt Enable CMPMx Comparison x Match Interrupt Enable CMPUx Comparison x Update Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 7 6 5 4 3 2 ...

Page 947: ...TX Buffer Interrupt Disable TXBUFE PDC TX Buffer Empty Interrupt Disable UNRE Synchronous Channels Update Underrun Error Interrupt Disable CMPMx Comparison x Match Interrupt Disable CMPUx Comparison x Update Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 7 6 5 4 ...

Page 948: ... of TX Buffer Interrupt Mask TXBUFE PDC TX Buffer Empty Interrupt Mask UNRE Synchronous Channels Update Underrun Error Interrupt Mask CMPMx Comparison x Match Interrupt Mask CMPUx Comparison x Update Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 7 6 5 4 3 2 1 0 UNR...

Page 949: ...Underrun Error 0 No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register 1 At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register CMPMx Comparison x Match 0 The comparison x has not matched since the last read of the PWM_ISR2 register 1 The comparison x has matched at least one time since the last read o...

Page 950: ...el x 0 Override value is 0 for PWMH output of channel x 1 Override value is 1 for PWMH output of channel x OOVLx Output Override Value for PWML output of the channel x 0 Override value is 0 for PWML output of channel x 1 Override value is 1 for PWML output of channel x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OOVL3 OOVL2 OOVL1 OOVL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OOVH3 OOVH2 OOVH1 OO...

Page 951: ...OHx selected as PWMH output of channel x 1 Output override value OOVHx selected as PWMH output of channel x OSLx Output Selection for PWML output of the channel x 0 Dead time generator output DTOLx selected as PWML output of channel x 1 Output override value OOVLx selected as PWML output of channel x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSL3 OSL2 OSL1 OSL0 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 952: ...MH output of the channel x 0 No effect 1 Output override value OOVHx selected as PWMH output of channel x OSSLx Output Selection Set for PWML output of the channel x 0 No effect 1 Output override value OOVLx selected as PWML output of channel x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSSL3 OSSL2 OSSL1 OSSL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSSH3 OSSH2 OSSH1 OSSH0 ...

Page 953: ...utput of the channel x 0 No effect 1 Dead time generator output DTOHx selected as PWMH output of channel x OSCLx Output Selection Clear for PWML output of the channel x 0 No effect 1 Dead time generator output DTOLx selected as PWML output of channel x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSCL3 OSCL2 OSCL1 OSCL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSCH3 OSCH2 OSCH1 OSCH0 ...

Page 954: ...ide value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period OSSUPLx Output Selection Set for PWML output of the channel x 0 No effect 1 Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSSUPL3 OSSUPL2 OSSUPL1 OSSUPL0 15 14 13 12 11 10 9 8 7 6 ...

Page 955: ...tor output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period OSCUPLx Output Selection Clear for PWML output of the channel x 0 No effect 1 Dead time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSCUPL3 OSCUPL2 OSCUPL1 OSCUPL0 15 14 13 12 11 10 ...

Page 956: ...nput number 0 The fault y is active until the Fault condition is removed at the peripheral 1 level 1 The fault y stays active until the Fault condition is removed at the peripheral 1 level AND until it is cleared in the PWM Fault Clear Register Note 1 The Peripheral generating the fault FFIL Fault Filtering fault input bit varies from 0 to 5 For each field bit y fault input number 0 The fault inpu...

Page 957: ... number 0 The current sampled value of the fault input y is 0 after filtering if enabled 1 The current sampled value of the fault input y is 1 after filtering if enabled FS Fault Status fault input bit varies from 0 to 5 For each field bit y fault input number 0 The fault y is not currently active 1 The fault y is currently active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 958: ...eld bit y fault input number 0 No effect 1 If bit y of FMOD field is set to 1 and if the fault input y is not at the level defined by the bit y of FPOL field the fault y is cleared and becomes inactive FMOD and FPOL fields belong to PWM Fault Mode Register on page 956 else writing this bit to 1 has no effect 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FCLR...

Page 959: ...ult Protection Value for PWMH output on channel x 0 PWMH output of channel x is forced to 0 when fault occurs 1 PWMH output of channel x is forced to 1 when fault occurs FPVLx Fault Protection Value for PWML output on channel x 0 PWML output of channel x is forced to 0 when fault occurs 1 PWML output of channel x is forced to 1 when fault occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FPVL...

Page 960: ... FPEx Fault Protection Enable for channel x fault input bit varies from 0 to 5 For each field bit y fault input number 0 Fault y is not used for the Fault Protection of channel x 1 Fault y is used for the Fault Protection of channel x CAUTION To prevent an unexpected activation of the Fault Protection the bit y of FPEx field can be set to 1 only if the corresponding FPOL bit has been previously co...

Page 961: ...ess Read write CSELy Comparison y Selection 0 A pulse is not generated on the event line x when the comparison y matches 1 A pulse is generated on the event line x when the comparison y match 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSEL7 CSEL6 CSEL5 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0 ...

Page 962: ...ad write GCENx Gray Count ENable 0 Disable gray count generation on PWML 2 x PWMH 2 x PWML 2 x 1 PWMH 2 x 1 1 enable gray count generation on PWML 2 x PWMH 2 x PWML 2 x 1 PWMH 2 x 1 DOWNx DOWN Count 0 Up counter 1 Down counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DOWN1 DOWN0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GCEN1 GCEN0 ...

Page 963: ... the PIO controller 3 No effect Note Only a hardware reset of the PWM controller can disable the Write Protect HW WPRGx Write Protect Register Group x 0 The WPCMD command has no effect on the register group x 1 The WPCMD command is applied to the register group x WPKEY Write Protect Key Should be written at value 0x50574D PWM in ASCII Writing any other value in this field aborts the write operatio...

Page 964: ...eriod Register on page 974 PWM Channel Period Update Register on page 975 Register group 4 PWM Channel Dead Time Register on page 977 PWM Channel Dead Time Update Register on page 978 Register group 5 PWM Fault Mode Register on page 956 PWM Fault Protection Value Register on page 959 ...

Page 965: ...WPSR register 1 At least one Write Protect violation has occurred since the last read of the PWM_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset in which a write access has ...

Page 966: ...ue to be compared with the counter of the channel 0 CVM Comparison x Value Mode 0 The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing 1 The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing Note This bit is useless if the counter of the channel 0 is ...

Page 967: ... compared with the counter of the channel 0 CVMUPD Comparison x Value Mode Update 0 The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing 1 The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing Note This bit is useless if the counter of the channel 0 i...

Page 968: ...efines the maximum value of the comparison x period counter CPRCNT The comparison x value is performed periodically once every CPR 1 periods of the channel 0 counter CPRCNT Comparison x Period Counter Reports the value of the comparison x period counter Note The field CPRCNT is read only CUPR Comparison x Update Period Defines the time between each update of the comparison x mode and the compariso...

Page 969: ...and can match CTRUPD Comparison x Trigger Update The comparison x is performed when the value of the comparison x period counter CPRCNT reaches the value defined by CTR CPRUPD Comparison x Period Update CPR defines the maximum value of the comparison x period counter CPRCNT The comparison x value is performed periodically once every CPR 1 periods of the channel 0 counter CUPRUPD Comparison x Updat...

Page 970: ...ut from the comparator starts at a low level 1 The OCx output waveform output from the comparator starts at a high level 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DTLI DTHI DTE 15 14 13 12 11 10 9 8 CES CPOL CALG 7 6 5 4 3 2 1 0 CPRE Value Name Description 0b0000 MCK Master clock 0b0001 MCK_DIV_2 Master clock 2 0b0010 MCK_DIV_4 Master clock 4 0b0011 MCK_DIV_8 Master clock 8 0b0100 MCK_DIV_16...

Page 971: ...G 1 Center Alignment 0 The channel counter event occurs at the end of the PWM period 1 The channel counter event occurs at the end of the PWM period and at half the PWM period DTE Dead Time Generator Enable 0 The dead time generator is disabled 1 The dead time generator is enabled DTHI Dead Time PWMHx Output Inverted 0 The dead time PWMHx output is not inverted 1 The dead time PWMHx output is inve...

Page 972: ...4 0 0x40020224 1 0x40020244 2 0x40020264 3 Access Read write Only the first 16 bits channel counter size are significant CDTY Channel Duty Cycle Defines the waveform duty cycle This value must be defined between 0 and CPRD PWM_CPRx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CDTY 15 14 13 12 11 10 9 8 CDTY 7 6 5 4 3 2 1 0 CDTY ...

Page 973: ...er acts as a double buffer for the CDTY value This prevents an unexpected waveform when modifying the wave form duty cycle Only the first 16 bits channel counter size are significant CDTYUPD Channel Duty Cycle Update Defines the waveform duty cycle This value must be defined between 0 and CPRD PWM_CPRx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CDTYUPD 15 14 13 12 11 10 9 8 CDTYUPD 7 6 5 4 3 ...

Page 974: ...ue with X being 1 2 4 8 16 32 64 128 256 512 or 1024 The resulting period formula will be By using the PWM master clock MCK divided by one of both DIVA or DIVB divider the formula becomes respectively or If the waveform is center aligned then the output waveform period depends on the channel counter source clock and can be calculated By using the PWM master clock MCK divided by an X given prescale...

Page 975: ... the PWM master clock MCK divided by an X given prescaler value with X being 1 2 4 8 16 32 64 128 256 512 or 1024 The resulting period formula will be By using the PWM master clock MCK divided by one of both DIVA or DIVB divider the formula becomes respectively or If the waveform is center aligned then the output waveform period depends on the channel counter source clock and can be calculated By ...

Page 976: ...e first 16 bits channel counter size are significant CNT Channel Counter Register Channel counter value This register is reset when the channel is enabled writing CHIDx in the PWM_ENA register the channel counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT ...

Page 977: ...ister on page 965 Only the first 12 bits dead time counter size of fields DTH and DTL are significant DTH Dead Time Value for PWMHx Output Defines the dead time value for PWMHx output This value must be defined between 0 and CPRD CDTY PWM_CPRx and PWM_CDTYx DTL Dead Time Value for PWMLx Output Defines the dead time value for PWMLx output This value must be defined between 0 and CDTY PWM_CDTYx 31 3...

Page 978: ... the first 12 bits dead time counter size of fields DTHUPD and DTLUPD are significant DTHUPD Dead Time Value Update for PWMHx Output Defines the dead time value for PWMHx output This value must be defined between 0 and CPRD CDTY PWM_CPRx and PWM_CDTYx This value is applied only at the beginning of the next channel x PWM period DTLUPD Dead Time Value Update for PWMLx Output Defines the dead time va...

Page 979: ...B device which notifies the proces sor by raising an interrupt Depending on the product an external signal can be used to send a wake up to the USB host controller 38 2 Embedded Characteristics USB V2 0 full speed compliant 12 Mbits per second Embedded USB V2 0 full speed transceiver Embedded 2688 byte dual port RAM for endpoints Eight endpoints Endpoint 0 64bytes Endpoint 1 and 2 64 bytes ping po...

Page 980: ...ws the UDP peripheral to wake up once in system mode The host is then notified that the device asks for a resume This optional feature must also be negotiated with the host during the enumeration 38 3 1 Signal Description Atmel Bridge 12 MHz Suspend Resume Logic W r a p p e r W r a p p e r U s e r I n t e r f a c e Serial Interface Engine SIE MCK Master Clock Domain Dual Port RAM FIFO UDPCK Recove...

Page 981: ...tion is activated and pins DDP and DDM are used for USB To configure DDP or DDM as PIOs the user needs to configure the system I O configuration register CCFG_SYSIO in the MATRIX 38 4 2 Power Management The USB device peripheral requires a 48 MHz clock This clock must be generated by a PLL with an accuracy of 0 25 Thus the USB device receives two clocks from the Power Management Controller PMC the...

Page 982: ... disabled in order to prevent powering the host through the pull up resistor When the host is disconnected and the transceiver is enabled then DDP and DDM are floating This may lead to over consumption A solution is to enable the integrated pulldown by disabling the transceiver TXVDIS 1 and then remove the pullup PUON 0 A termination serial resistor must be connected to DDP and DDM The resistor va...

Page 983: ...Data IN Transaction 3 Data OUT Transaction EP0 USB Host V2 0 Software Client 1 Software Client 2 Data Flow Bulk Out Transfer Data Flow Bulk In Transfer Data Flow Control Transfer Data Flow Control Transfer EP1 EP2 USB Device 2 0 Block 1 USB Device 2 0 Block 2 EP5 EP4 EP0 Data Flow Isochronous In Transfer Data Flow Isochronous Out Transfer USB Device endpoint configuration requires that in the firs...

Page 984: ...quence read or write the USB device sends or receives a status transaction Table 38 5 USB Transfer Events Control Transfers 1 3 Setup transaction Data IN transactions Status OUT transaction Setup transaction Data OUT transactions Status IN transaction Setup transaction Status IN transaction Interrupt IN Transfer device toward host Data IN transaction Data IN transaction Interrupt OUT Transfer host...

Page 985: ... to the device by a Data OUT transaction which follows the setup transaction These requests may also return data The data is carried out to the host by the next Data IN transaction which follows the setup transaction A status transaction ends the control transfer When a setup transfer is received by the USB endpoint The USB device automatically acknowledges the setup packet RXSETUP is set in the U...

Page 986: ...P in the endpoint s UDP_CSRx register has been set Then an interrupt for the corresponding endpoint is pending while TXCOMP is set 5 The microcontroller writes the second packet of data to be sent in the endpoint s FIFO writing zero or more byte values in the endpoint s UDP_FDRx register 6 The microcontroller notifies the USB peripheral it has finished by setting the TXPK TRDY in the endpoint s UD...

Page 987: ...apping Data IN Transfer for Ping pong Endpoints USB Bus Packets Data IN 2 Data IN NAK ACK Data IN 1 FIFO DPR Content Data IN 2 Load In Progress Data IN 1 Cleared by Firmware DPR access by the firmware Payload in FIFO TXCOMP Flag UDP_CSRx TXPKTRDY Flag UDP_CSRx PID Data IN Data IN PID PID PID PID ACK PID Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus Interrupt Pending ...

Page 988: ... USB device that it has prepared the second Bank to be sent raising TXPKTRDY in the end point s UDP_CSRx register 7 At this step Bank 0 is available and the microcontroller can prepare a third data pay load to be sent Figure 38 9 Data IN Transfer for Ping pong Endpoint Warning There is software critical path due to the fact that once the second bank is filled the driver has to wait for TX_COMP to ...

Page 989: ...received is available by reading the endpoint s UDP_FDRx register 6 The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint s UDP_CSRx register 7 A new Data OUT packet can be accepted by the USB device Figure 38 10 Data OUT Transfer for Non Ping pong Endpoints An interrupt is pending while the flag RX_DATA_BK0 is set Memory transfer bet...

Page 990: ...er 6 The microcontroller transfers out data received from the endpoint s memory to the microcontroller s memory Data received is made available by reading the endpoint s UDP_FDRx register 7 The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint s UDP_CSRx register 8 A third Data OUT packet can be accepted by the USB peripher...

Page 991: ...us Specification Rev 2 0 A functional stall is used when the halt feature associated with the endpoint is set Refer to Chapter 9 of the Universal Serial Bus Specification Rev 2 0 for more information on the halt feature To abort the current request a protocol stall is used but uniquely with control transfer The following procedure generates a stall packet 1 The microcontroller sets the FORCESTALL ...

Page 992: ...s received after a stall handshake STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set Figure 38 13 Stall Handshake Data IN Transfer Figure 38 14 Stall Handshake Data OUT Transfer Data IN Stall PID PID USB Bus Packets Cleared by Firmware Set by Firmware FORCESTALL STALLSENT Set by USB Device Cleared by Firmware Interrupt Pending Data OUT PID Stall PID Data OUT USB B...

Page 993: ...ion 38 7 9 UDP Reset Endpoint Register TXPKTRDY has already been set Clear TXPKTRDY so that no packet is ready to be sent Reset the endpoint to clear the FIFO pointers See Section 38 7 9 UDP Reset Endpoint Register Endpoints With Dual Banks There are two possibilities In one case TXPKTRDY field in UDP_CSR has already been set In the other instance TXPKTRDY is not set TXPKTRDY is not set Reset the ...

Page 994: ...ry Constraints in Suspend Mode are very strict for bus powered applications devices may not consume more than 500 µA on the USB bus While in Suspend Mode the host may wake up a device by sending a resume signal bus activ ity or a USB device may send a wake up request to the host e g waking up a PC by moving a USB mouse The wake up feature is not mandatory for all devices and must be negotiated wit...

Page 995: ...DP_IER register The enumeration then begins by a control transfer Configure the interrupt mask register which has been reset by the USB reset detection Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register In this state UDPCK and MCK must be enabled Warning Each time an ENDBUSRES interrupt is triggered the Interrupt Mask Register and UDP_CSR registers have been reset 38 6 3 4 Fr...

Page 996: ...P signal in the UDP_ISR is set It may gen erate an interrupt if the corresponding bit in the UDP_IMR register is set This interrupt may be used to wake up the core enable PLL and main oscillators and configure clocks Warning Read write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_...

Page 997: ...ead write 0x0000_0100 0x00C Reserved 0x010 Interrupt Enable Register UDP_IER Write only 0x014 Interrupt Disable Register UDP_IDR Write only 0x018 Interrupt Mask Register UDP_IMR Read only 0x0000_1200 0x01C Interrupt Status Register UDP_ISR Read only 1 0x020 Interrupt Clear Register UDP_ICR Write only 0x024 Reserved 0x028 Reset Endpoint Register UDP_RST_EP Read write 0x0000_0000 0x02C Reserved 0x03...

Page 998: ...et at SOF_EOP when the SOF packet is received containing an error This bit is reset upon receipt of SOF_PID FRM_OK Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error This bit is reset upon receipt of SOF_PID Packet Identification In the Interrupt Status Register the SOF interrupt is updated upon receiving SOF_PID This bit is set without waiting for EOP Note In th...

Page 999: ...o chapter 9 of the Universal Serial Bus Specification Rev 2 0 for more details CONFG Configured Read 0 Device is not in configured state 1 Device is in configured state Write 0 Sets device in a non configured state 1 Sets device in configured state The device is set in configured state when it is in address state and receives a successful Set Configuration request Refer to Chapter 9 of the Univers...

Page 1000: ...ication Rev 2 0 for more information After power up or reset the function address value is set to 0 FEN Function Enable Read 0 Function endpoint disabled 1 Function endpoint enabled Write 0 Disables function endpoint 1 Default value The Function Enable bit FEN allows the microcontroller to enable or disable the function endpoints The microcontroller sets this bit after receipt of a reset from the ...

Page 1001: ...P7INT Enable Endpoint 7 Interrupt 0 No effect 1 Enables corresponding Endpoint Interrupt RXSUSP Enable UDP Suspend Interrupt 0 No effect 1 Enables UDP Suspend Interrupt RXRSM Enable UDP Resume Interrupt 0 No effect 1 Enables UDP Resume Interrupt SOFINT Enable Start Of Frame Interrupt 0 No effect 1 Enables Start Of Frame Interrupt WAKEUP Enable UDP bus Wakeup Interrupt 0 No effect 1 Enables USB bus...

Page 1002: ...P7INT Disable Endpoint 7 Interrupt 0 No effect 1 Disables corresponding Endpoint Interrupt RXSUSP Disable UDP Suspend Interrupt 0 No effect 1 Disables UDP Suspend Interrupt RXRSM Disable UDP Resume Interrupt 0 No effect 1 Disables UDP Resume Interrupt SOFINT Disable Start Of Frame Interrupt 0 No effect 1 Disables Start Of Frame Interrupt WAKEUP Disable USB Bus Interrupt 0 No effect 1 Disables USB ...

Page 1003: ...s disabled 1 Corresponding Endpoint Interrupt is enabled RXSUSP Mask UDP Suspend Interrupt 0 UDP Suspend Interrupt is disabled 1 UDP Suspend Interrupt is enabled RXRSM Mask UDP Resume Interrupt 0 UDP Resume Interrupt is disabled 1 UDP Resume Interrupt is enabled SOFINT Mask Start Of Frame Interrupt 0 Start of Frame Interrupt is disabled 1 Start of Frame Interrupt is enabled BIT12 UDP_IMR Bit 12 Bi...

Page 1004: ...nterrupt is disabled 1 USB Bus Wakeup Interrupt is enabled Note When the USB block is in suspend mode the application may power down the USB logic In this case any USB HOST resume request that is made must be taken into account and thus the reset value of the RXRSM bit of the register UDP_IMR is enabled ...

Page 1005: ...veral signals can generate this interrupt The reason can be found by reading UDP_CSR0 RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit RXSUSP UDP Suspend Interrupt Status 0 No UDP Suspend Interrupt pending 1 UDP Suspend Interrupt has been ...

Page 1006: ... each time a SOF token has been detected It can be used as a synchronization signal by using isochronous endpoints ENDBUSRES End of BUS Reset Interrupt Status 0 No End of Bus Reset Interrupt pending 1 End of Bus Reset Interrupt has been raised This interrupt is raised at the end of a UDP reset sequence The USB device must prepare to receive requests on the end point 0 The host starts the enumerati...

Page 1007: ...P Resume Interrupt 0 No effect 1 Clears UDP Resume Interrupt SOFINT Clear Start Of Frame Interrupt 0 No effect 1 Clears Start Of Frame Interrupt ENDBUSRES Clear End of Bus Reset Interrupt 0 No effect 1 Clears End of Bus Reset Interrupt WAKEUP Clear Wakeup Interrupt 0 No effect 1 Clears Wakeup Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WAKEUP ENDBUSRES SOFINT EX...

Page 1008: ... It also resets the data toggle to DATA0 It is useful after removing a HALT condition on a BULK endpoint Refer to Chapter 5 8 5 in the USB Serial Bus Specification Rev 2 0 Warning This flag must be cleared at the end of the reset It does not clear UDP_CSRx flags 0 No reset 1 Forces the corresponding endpoint FIF0 pointers to 0 therefore RXBYTECNT field is read at 0 in UDP_CSRx register Resetting t...

Page 1009: ... are not effected by a value 1 define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0 AT91C_UDP_RX_DATA_BK1 AT91C_UDP_STALLSENT AT91C_UDP_RXSETUP AT91C_UDP_TXCOMP Sets the specified bit s in the UDP_CSR register param endpoint The endpoint number of the CSR to process param flags The bitmap to set to 1 define SET_CSR endpoint flags volatile unsigned int reg reg AT91C_BASE_UDP UDP_CSR endpoint reg REG_NO...

Page 1010: ...d by the firmware 0 Clear the flag clear the interrupt 1 No effect Read Set by the USB peripheral 0 Data IN transaction has not been acknowledged by the Host 1 Data IN transaction is achieved acknowledged by the Host After having issued a Data IN transaction setting TXPKTRDY the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction RX_DATA_BK0 Receive Data Bank...

Page 1011: ...etup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory Once a transfer has been done RXSETUP must be cleared by the device firmware Ensuing Data OUT transaction is not accepted while RXSETUP is set STALLSENT Stall Sent Control Bulk Interrupt Endpoints ISOERROR Isochronous Endpoints This flag generates an interrupt while it is set to one STALLSENT This ends a STALL h...

Page 1012: ...ng or clearing this bit a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR FORCESTALL Force Stall used by Control Bulk and Isochronous Endpoints Read 0 Normal state 1 Stall state Write 0 Return to normal state 1 Send STALL to the host Refer to chapters 8 4 5 and 9 4 5 of the Universal Serial Bus Specification Rev 2 0 for more information on the STALL...

Page 1013: ...r 8 5 3 of the Universal Serial Bus Specification Rev 2 0 for more information on the control data stage This bit must be set before UDP_CSRx RXSETUP is cleared at the end of the setup stage According to the request sent in the setup data packet the data stage is either a device to host DIR 1 or host to device DIR 0 data transfer It is not necessary to check this bit to reverse direction for the s...

Page 1014: ... After reset all endpoints are configured as control endpoints zero RXBYTECNT 10 0 Number of Bytes Available in the FIFO Read only When the host sends a data packet to the device the USB device stores the data in the FIFO and notifies the microcon troller The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register ...

Page 1015: ... in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO sent by the host The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor It can not be more than the physical memory size associated to the endpoint Refer to the Universal Serial Bus Specification Rev 2 0 for more information 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 1016: ...ntly by disabling the embedded transceiver This can be done by setting TXVDIS field To enable the transceiver TXVDIS must be cleared PUON Pullup On 0 The 1 5KΩ integrated pullup on DDP is disconnected 1 The 1 5 KΩ integrated pullup on DDP is connected NOTE If the USB pullup is not connected on DDP the user should not write in any UDP register other than the UDP_TXVC register This is because if DDP...

Page 1017: ... and the result of this comparison gives a com pare output The user can select a high speed or low power option Additionally the hysteresis level edge detection and polarity are configurable The ACC can also generate a compare event which can be used by the PWM Refer to Figure 39 1 on page 1018 for detailed schematics 39 2 Embedded Characteristics 8 User Analog Inputs Selectable for Comparison 4 V...

Page 1018: ...or Controller Block Diagram Mux AD7 AD0 Mux TS AD3 ADVREF DAC0 DAC1 AD0 inp inn Analog Comparator isel oncomp hyst bias AND AND MCK Synchro Edge Detect ACC_MR ACC_ACR Change Detect Mask Timer INV SELMINUS SELPLUS ACEN EDGETYP SCO CE MASK SELFS SCO MCK HYST ISEL Interrupt Controller FE User Interface ...

Page 1019: ...y 39 4 Pin Name List Table 39 1 ACC Pin List Pin Name Description Type AD0 AD7 Analog Inputs Input TS On Chip Temperature Sensor Input ADVREF ADC Voltage Reference Input DAC0 DAC1 On Chip DAC Outputs Input FAULT Drives internal fault input of PWM Output ...

Page 1020: ...Controller PMC thus the programmer must first configure the PMC to enable the Analog Comparator Controller clock Note that the voltage regulator needs to be activated to use the Analog Comparator 39 5 3 Interrupt The ACC has an interrupt line connected to the Interrupt Controller IC Handling the ACC inter rupt requires programming the Interrupt Controller before configuring the ACC 39 5 4 Fault Ou...

Page 1021: ...C Analog Control Regis ter When this mode is enabled and one of the protected registers is written the register write request is canceled Due to the nature of the write protection feature enabling and disabling the write protection mode requires a security code Thus when enabling or disabling the write protection mode the WPKEY field of the ACC_WPMR register must be filled with the ACC ASCII code ...

Page 1022: ...x08 0x20 Reserved 0x24 Interrupt Enable Register ACC_IER Write only 0x28 Interrupt Disable Register ACC_IDR Write only 0x2C Interrupt Mask Register ACC_IMR Read only 0 0x30 Interrupt Status Register ACC_ISR Read only 0 0x34 0x90 Reserved 0x94 Analog Control Register ACC_ACR Read write 0 0x98 0xE0 Reserved 0xE4 Write Protect Mode Register ACC_WPMR Read write 0 0xE8 Write Protect Status Register ACC...

Page 1023: ...ries Preliminary 39 7 1 ACC Control Register Name ACC_CR Address 0x40040000 Access Write only SWRST SoftWare ReSeT 0 No effect 1 Resets the module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST ...

Page 1024: ...ster SELMINUS SELection for MINUS comparator input 0 7 Selects the input to apply on analog comparator SELMINUS comparison input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FE SELFS INV EDGETYP ACEN 7 6 5 4 3 2 1 0 SELPLUS SELMINUS Value Name Description 0 TS SelectTS 1 ADVREF Select ADVREF 2 DAC0 Select DAC0 3 DAC1 Select DAC1 4 AD0 Select AD0 5 AD1 Select AD1 6 AD2 Sele...

Page 1025: ...ior to being processed SELFS SELection of Fault Source 0 CF The CF flag is used to drive the FAULT output 1 OUTPUT The output of the Analog Comparator flag is used to drive the FAULT output FE Fault Enable 0 DIS The FAULT output is tied to 0 1 EN The FAULT output is driven by the signal defined by SELFS Value Name Description 0 AD0 Select AD0 1 AD1 Select AD1 2 AD2 Select AD2 3 AD3 Select AD3 4 AD...

Page 1026: ...errupt Enable Register Name ACC_IER Address 0x40040024 Access Write only CE Comparison Edge 0 No effect 1 Enables the interruption when the selected edge defined by EDGETYP occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE ...

Page 1027: ...rrupt Disable Register Name ACC_IDR Address 0x40040028 Access Write only CE Comparison Edge 0 No effect 1 Disables the interruption when the selected edge defined by EDGETYP occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE ...

Page 1028: ... 39 7 5 ACC Interrupt Mask Register Name ACC_IMR Address 0x4004002C Access Read only CE Comparison Edge 0 The interruption is disabled 1 The interruption is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE ...

Page 1029: ...fined by EDGETYP on analog comparator output occurred since the last read of ACC_ISR register SCO Synchronized Comparator Output Returns an image of Analog Comparator Output after being pre processed refer to Figure 39 1 on page 1018 If INV 0 SCO 0 if inn inp SCO 1 if inp inn If INV 1 SCO 1 if inn inp SCO 0 if inp inn MASK 0 The CE flag is valid 1 The CE flag and SCO value are invalid 31 30 29 28 ...

Page 1030: ...written if the WPEN bit is cleared in ACC Write Protect Mode Register ISEL Current SELection Refer to the product Electrical Characteristics 0 LOPW Low power option 1 HISP High speed option HYST HYSTeresis selection 0 to 3 Refer to the product Electrical Characteristics 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HYST ISEL ...

Page 1031: ...ables the Write Protect if WPKEY corresponds to 0x414343 ACC in ASCII Protects the registers ACC Mode Register on page 1024 ACC Analog Control Register on page 1030 WPKEY Write Protect KEY This security code is needed to set reset the WPROT bit value see Section 39 6 3 Write Protection System for details Must be filled with ACC ASCII code 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY...

Page 1032: ...E8 Access Read only WPROTERR Write PROTection ERRor 0 No Write Protect Violation has occurred since the last read of the ACC_WPSR register 1 A Write Protect Violation WPEN 1 has occurred since the last read of the ACC_WPSR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WPROTERR ...

Page 1033: ...rison circuitry in order to immediately put the PWM outputs in a safe state pure combinational path The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel These features reduce both power consumption and processor intervention This ADC has a selectable single ended or fully differential input and benefits from a 2 bit pro grammable gain A whole set of refer...

Page 1034: ...rted when necessary Configuring the ADC Controller does not require the ADC Controller clock to be enabled 40 5 2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller Using the ADC interrupt requires the interrupt controller to be programmed first Table 40 1 ADC Pin Description Pin Name Description ADVREF Reference voltage AD0 AD15 1 Anal...

Page 1035: ...of the temperature sensor must be achieved prior to initiating any measure 40 5 5 I O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller In this case the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function 40 5 6 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements Thus so...

Page 1036: ...ANSFER of the same register The ADC Clock frequency is selected in the PRESCAL field of the Mode Reg ister ADC_MR The tracking phase starts during the conversion of the previous channel If the tracking time is longer than the conversion time the tracking phase is extended to the end of the previous conversion The ADC clock range is between MCK 2 if PRESCAL is 0 and MCK 512 if PRESCAL is set to 255...

Page 1037: ...he ADC 12 bit or 10 bit resolution sets the transfer request size to 16 bits 40 6 4 Conversion Results When a conversion is completed the resulting 12 bit digital value is stored in the Channel Data Register ADC_CDRx of the current channel and in the ADC Last Converted Data Register ADC_LCDR By setting the TAG option in the ADC_EMR the ADC_LCDR presents the chan nel number associated to the last c...

Page 1038: ...lag is set in the Overrun Status Register ADC_OVER Likewise new data converted when DRDY is high sets the GOVRE bit General Overrun Error in ADC_SR The OVREx flag is automatically cleared when ADC_OVER is read and GOVRE flag is auto matically cleared when ADC_SR is read Read the ADC_CDRx EOCx DRDY Read the ADC_LCDR CHx ADC_CHSR ADC_SR ADC_SR Write the ADC_CR with START 1 Write the ADC_CR with STAR...

Page 1039: ...rsion its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable EOC0 GOVRE CH0 ADC_CHSR ADC_SR ADC_SR Trigger event EOC1 CH1 ADC_CHSR ADC_SR OVRE0 ADC_OVER Undefined Data Data A Data B ADC_LCDR Undefined Data Data A ADC_CDR0 Undefined Data Data B ADC_CDR1 Data C Data C Conversion C Conversion A DRDY ADC_SR Read ADC_CDR1 Read ADC_CDR0 Conversion B Read ADC_OVER Read A...

Page 1040: ... disabled independently If the ADC is used with a PDC only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly 40 6 6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions Sleep Mode is selected by setting the SLEEP...

Page 1041: ...ited by this behavior As an example if only 4 channels over 16 CH0 up to CH3 are selected for ADC conversions the user sequence length cannot exceed 4 channels Each trigger event may launch up to 4 suc cessive conversions of any combination of channels 0 up to 3 but no more i e in this case the sequence CH0 CH0 CH1 CH1 CH1 is impossible A sequence that repeats several times the same channel requir...

Page 1042: ...ingle ended or differential mode In single ended mode inputs are managed by a 16 1 channels analog multiplexer In the fully differential mode inputs are managed by an 8 1 channels analog multiplexer See Table 40 4 and Table 40 5 Table 40 4 Input Pins and Channel Number in Single Ended Mode Input Pins Channel Number AD0 CH0 AD1 CH1 AD2 CH2 AD3 CH3 AD4 CH4 AD5 CH5 AD6 CH6 AD7 CH7 AD8 CH8 AD9 CH9 AD1...

Page 1043: ...fset on each channel Oth erwise the parameters of CH0 are applied to all channels The gain is configurable through the GAIN bit of the Channel Gain Register ADC_CGR as shown in Table 40 6 To allow full range analog offset of the ADC can be configured by the OFFSET bit of the Chan nel Offset Register ADC_COR The Offset is only available in Single Ended Mode Table 40 6 Gain of the Sample and Hold Un...

Page 1044: ...ADC to guarantee the best converted final value between two channel selections This time has to be programmed through the TRACKTIM bit field in the Mode Register ADC_MR VIN gain 0 5 gain 1 gain 2 gain 4 single ended se0fd1 0 fully differential se0fd1 1 same as gain 1 same as gain 2 0 vrefin vrefin vrefin 0 vrefin vrefin vrefin vrefin 0 5 8 vrefin 3 8 vrefin vrefin offset 0 offset 1 offset 0 offset...

Page 1045: ...ADC_COR registers for a given channel are changed the AUTOCALIB sequence must then be started again The calibration data on one or more enabled channels is stored in the internal ADC memory Then when a new conversion is started on one or more enabled channels the converted value in ADC_LCDR or ADC_CDRx registers is a calibrated value Autocalibration is for settings not for channels Therefore if a ...

Page 1046: ...ust be FMOD 1 40 6 14 Write Protected Registers To prevent any single software error that may corrupt ADC behavior certain address spaces can be write protected by setting the WPEN bit in the ADC Write Protect Mode Register ADC_WPMR If a write access to the protected registers is detected then the WPVS flag in the ADC Write Pro tect Status Register ADC_WPSR is set and the field WPVSRC indicates in...

Page 1047: ...le Register ADC_IER Write only 0x28 Interrupt Disable Register ADC_IDR Write only 0x2C Interrupt Mask Register ADC_IMR Read only 0x00000000 0x30 Interrupt Status Register ADC_ISR Read only 0x00000000 0x3C Overrun Status Register ADC_OVER Read only 0x00000000 0x40 Extended Mode Register ADC_EMR Read write 0x00000000 0x44 Compare Window Register ADC_CWR Read write 0x00000000 0x48 Channel Gain Regist...

Page 1048: ... 0 No effect 1 Resets the ADC simulating a hardware reset START Start Conversion 0 No effect 1 Begins analog to digital conversion AUTOCAL Automatic Calibration of ADC 0 No effect 1 Launch an automatic calibration of the ADC cell on next sequence 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AUTOCAL START SWRST ...

Page 1049: ...8 PRESCAL 7 6 5 4 3 2 1 0 FREERUN FWUP SLEEP LOWRES TRGSEL TRGEN Value Name Description 0 DIS Hardware triggers are disabled Starting a conversion is only possible by software 1 EN Hardware trigger selected by TRGSEL field is enabled Value Name Description 0 ADC_TRIG0 External trigger 1 ADC_TRIG1 TIO Output of the Timer Counter Channel 0 2 ADC_TRIG2 TIO Output of the Timer Counter Channel 1 3 ADC_...

Page 1050: ... Up Sleep Mode The Voltage reference is ON between conversions and ADC Core is OFF Value Name Description 0 OFF Normal Mode 1 ON Free Run Mode Never wait for any trigger Value Name Description 0 SUT0 0 periods of ADCClock 1 SUT8 8 periods of ADCClock 2 SUT16 16 periods of ADCClock 3 SUT24 24 periods of ADCClock 4 SUT64 64 periods of ADCClock 5 SUT80 80 periods of ADCClock 6 SUT96 96 periods of ADC...

Page 1051: ...ds of ADCClock 3 AST17 17 periods of ADCClock Value Name Description 0 NONE No analog change on channel switching DIFF0 GAIN0 and OFF0 are used for all channels 1 ALLOWED Allows different analog settings for each channel See ADC_CGR and ADC_COR Registers Value Name Description 0 NUM_ORDER Normal Mode The controller converts channels in a simple numeric order depending only on the channel index 1 R...

Page 1052: ...ield is set to 1 Any USCHx field is taken into account only if ADC_CHSR CHx register field reads logical 1 else any value written in USCHx does not add the corresponding channel in the conversion sequence When configuring consecutive fields with the same value the associated channel is sampled as many time as the number of consecutive values this part of the conversion sequence being triggered by ...

Page 1053: ...d is set to 1 Any USCHx field is taken into account only if ADC_CHSR CHx register field reads logical 1 else any value written in USCHx does not add the corresponding channel in the conversion sequence When configuring consecutive fields with the same value the associated channel is sampled as many time as the number of consecutive values this part of the conversion sequence being triggered by a u...

Page 1054: ...red in ADC Write Protect Mode Register on page 1069 CHx Channel x Enable 0 No effect 1 Enables the corresponding channel Note if USEQ 1 in ADC_MR register CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and ADC_SEQR2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 ...

Page 1055: ...1069 CHx Channel x Disable 0 No effect 1 Disables the corresponding channel Warning If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver sion its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 7...

Page 1056: ... ADC_CHSR Address 0x40038018 Access Read only CHx Channel x Status 0 Corresponding channel is disabled 1 Corresponding channel is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 ...

Page 1057: ...o digital conversion data is placed into this register at the end of a conversion and remains until a new conver sion is completed CHNB Channel Number Indicates the last converted channel when the TAG option is set to 1 in the ADC_EMR register If the TAG option is not set CHNB 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHNB LDATA 7 6 5 4 3 2 1 0 LDATA ...

Page 1058: ...pt Enable GOVRE General Overrun Error Interrupt Enable COMPE Comparison Event Interrupt Enable ENDRX End of Receive Buffer Interrupt Enable RXBUFF Receive Buffer Full Interrupt Enable 0 No effect 1 Enables the corresponding interrupt 31 30 29 28 27 26 25 24 RXBUFF ENDRX COMPE GOVRE DRDY 23 22 21 20 19 18 17 16 EOCAL 15 14 13 12 11 10 9 8 EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8 7 6 5 4 3 2 1 ...

Page 1059: ... Disable GOVRE General Overrun Error Interrupt Disable COMPE Comparison Event Interrupt Disable ENDRX End of Receive Buffer Interrupt Disable RXBUFF Receive Buffer Full Interrupt Disable 0 No effect 1 Disables the corresponding interrupt 31 30 29 28 27 26 25 24 RXBUFF ENDRX COMPE GOVRE DRDY 23 22 21 20 19 18 17 16 EOCAL 15 14 13 12 11 10 9 8 EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8 7 6 5 4 3 ...

Page 1060: ...General Overrun Error Interrupt Mask COMPE Comparison Event Interrupt Mask ENDRX End of Receive Buffer Interrupt Mask RXBUFF Receive Buffer Full Interrupt Mask 0 The corresponding interrupt is disabled 1 The corresponding interrupt is enabled 31 30 29 28 27 26 25 24 RXBUFF ENDRX COMPE GOVRE DRDY 23 22 21 20 19 18 17 16 EOCAL 15 14 13 12 11 10 9 8 EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8 7 6 5...

Page 1061: ...al Overrun Error 0 No General Overrun Error occurred since the last read of ADC_ISR 1 At least one General Overrun Error has occurred since the last read of ADC_ISR COMPE Comparison Error 0 No Comparison Error since the last read of ADC_ISR 1 At least one Comparison Error defined in the ADC_EMR and ADC_CWR registers has occurred since the last read of ADC_ISR ENDRX End of RX Buffer 0 The Receive C...

Page 1062: ...0 No overrun error on the corresponding channel since the last read of ADC_OVER 1 There has been an overrun error on the corresponding channel since the last read of ADC_OVER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 OVRE15 OVRE14 OVRE13 OVRE12 OVRE11 OVRE10 OVRE9 OVRE8 7 6 5 4 3 2 1 0 OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 ...

Page 1063: ...s compared 1 All channels are compared TAG TAG of the ADC_LDCR register 0 Set CHNB to zero in ADC_LDCR 1 Append the channel number to the conversion result in ADC_LDCR register 31 30 29 28 27 26 25 24 TAG 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CMPALL 7 6 5 4 3 2 1 0 CMPSEL CMPMODE Value Name Description 0 LOW Generates an event when the converted data is lower than the low threshold of the ...

Page 1064: ...f LOWRES is set in ADC_MR only the 12 LSB of LOWTHRES must be programmed The 2 LSB will be automatically dis carded to match the value carried on ADC_CDR 10 bit HIGHTHRES High Threshold High threshold associated to compare settings of the ADC_EMR register If LOWRES is set in ADC_MR only the 12 LSB of HIGHTHRES must be programmed The 2 LSB will be automatically dis carded to match the value carried...

Page 1065: ...1069 GAINx Gain for channel x Gain applied on input of analog to digital converter The DIFFx mentioned in this table is described in the following register ADC_COR 31 30 29 28 27 26 25 24 GAIN15 GAIN14 GAIN13 GAIN12 23 22 21 20 19 18 17 16 GAIN11 GAIN10 GAIN9 GAIN8 15 14 13 12 11 10 9 8 GAIN7 GAIN6 GAIN5 GAIN4 7 6 5 4 3 2 1 0 GAIN3 GAIN2 GAIN1 GAIN0 GAINx Gain applied when DIFFx 0 Gain applied whe...

Page 1066: ...og signal on Vrefin 2 before the gain scaling The Offset applied is G 1 Vrefin 2 where G is the gain applied see description of ADC_CGR register DIFFx Differential inputs for channel x 0 Single Ended Mode 1 Fully Differential Mode 31 30 29 28 27 26 25 24 DIFF15 DIFF14 DIFF13 DIFF12 DIFF11 DIFF10 DIFF9 DIFF8 23 22 21 20 19 18 17 16 DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 15 14 13 12 11 10 9...

Page 1067: ...TA Converted Data The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new conver sion is completed The Convert Data Register CDR is only loaded if the corresponding analog channel is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA ...

Page 1068: ...it is cleared in ADC Write Protect Mode Register on page 1069 TSON Temperature Sensor On 0 Temperature sensor is off 1 Temperature sensor is on IBCTL ADC Bias Current Control Allows to adapt performance versus power consumption See the product electrical characteristics for further details 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 IBCTL 7 6 5 4 3 2 1 0 TSON ...

Page 1069: ...1052 ADC Channel Sequence 2 Register on page 1053 ADC Channel Enable Register on page 1054 ADC Channel Disable Register on page 1055 ADC Extended Mode Register on page 1063 ADC Compare Window Register on page 1064 ADC Channel Gain Register on page 1065 ADC Channel Offset Register on page 1066 ADC Analog Control Register on page 1068 WPKEY Write Protect KEY Should be written at value 0x414443 ADC i...

Page 1070: ...since the last read of the ADC_WPSR register If this violation is an unauthor ized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Protect Violation Source When WPVS is active this field indicates the write protected register through address offset or code in which a write access has been attempted Reading ADC_WPSR automatically clears all ...

Page 1071: ...nfigurable The DACC integrates a Sleep Mode and connects with a PDC channel These features reduce both power consumption and processor intervention The user can configure DACC timings such as Startup Time and Refresh Period 41 2 Embedded Characteristics Up to 2 channel 12 bit DAC Up to 2 mega samples conversion rate in single channel mode Flexible conversion range Multiple trigger sources for each...

Page 1072: ...1 3 Block Diagram Figure 41 1 Digital to Analog Converter Controller Block Diagram DAC0 DAC1 AHB Analog Cell DAC Controller Control Logic Interrupt Controller PDC Peripheral Bridge APB User Interface Sample Hold Sample Hold Trigger Selection DATRG DAC Core ...

Page 1073: ...s This clock is named DACC Clock Once a conversion starts the DACC takes 25 clock periods to provide the analog result on the selected analog output 41 6 2 Conversion Results When a conversion is completed the resulting analog value is available at the selected DACC channel output and the EOC bit in the DACC Interrupt Status Register is set Reading the DACC_ISR register clears the EOC bit 41 6 3 C...

Page 1074: ...eans by which to select the channel to perform data conversion By default to select the channel where to convert the data is to use the USER_SEL field of the DACC Mode Register Data requests will merely be converted to the channel selected with the USER_SEL field A more flexible option to select the channel for the data to be converted to is to use the tag mode setting the TAG field of the DACC Mo...

Page 1075: ...lock periods between each consecutive conversion Warning Using this mode the EOC interrupt of the DACC_IER register should not be used as it is 2 DACC Clock periods late After 20 µs the analog voltage resulting from the converted data will start decreasing therefore it is necessary to refresh the channel on a regular basis to prevent this voltage loss This is the purpose of the REFRESH field in th...

Page 1076: ...urs the WPROTERR flag is set and the address of the corresponding canceled register write is available in the WPROTADRR field of the DACC Write Protect Status Register Due to the nature of the write protection feature enabling and disabling the write protection mode requires the use of a security code Thus when enabling or disabling the write protection mode the WPKEY field of the DACC Write Prote...

Page 1077: ...CHDR Write only 0x18 Channel Status Register DACC_CHSR Read only 0x00000000 0x1C Reserved 0x20 Conversion Data Register DACC_CDR Write only 0x00000000 0x24 Interrupt Enable Register DACC_IER Write only 0x28 Interrupt Disable Register DACC_IDR Write only 0x2C Interrupt Mask Register DACC_IMR Read only 0x00000000 0x30 Interrupt Status Register DACC_ISR Read only 0x00000000 0x94 Analog Current Regist...

Page 1078: ...ry 41 7 1 DACC Control Register Name DACC_CR Address 0x4003C000 Access Write only SWRST Software Reset 0 No effect 1 Resets the DACC simulating a hardware reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST ...

Page 1079: ...XS TAG USER_SEL 15 14 13 12 11 10 9 8 REFRESH 7 6 5 4 3 2 1 0 FASTWKUP SLEEP WORD TRGSEL TRGEN Value Name Description 0 DIS External trigger mode disabled DACC in free running mode 1 EN External trigger mode enabled TRGSEL Selected TRGSEL 0 0 0 External trigger 0 0 1 TIO Output of the Timer Counter Channel 0 0 1 0 TIO Output of the Timer Counter Channel 1 0 1 1 TIO Output of the Timer Counter Chan...

Page 1080: ...ode 0 Normal Sleep Mode The sleep mode is defined by the SLEEP bit 1 Fast Wake Up Sleep Mode The voltage reference is ON between conversions and DAC Core is OFF REFRESH Refresh Period Refresh Period 1024 REFRESH DACC Clock USER_SEL User Channel Selection TAG Tag Selection Mode MAXS Max Speed Mode SLEEP Selected Mode 0 Normal Mode 1 Sleep Mode FASTWKUP Selected Mode 0 Normal Sleep Mode 1 Fast Wake ...

Page 1081: ...eriods of DACClock 45 2880 2880 periods of DACClock 14 896 896 periods of DACClock 46 2944 2944 periods of DACClock 15 960 960 periods of DACClock 47 3008 3008 periods of DACClock 16 1024 1024 periods of DACClock 48 3072 3072 periods of DACClock 17 1088 1088 periods of DACClock 49 3136 3136 periods of DACClock 18 1152 1152 periods of DACClock 50 3200 3200 periods of DACClock 19 1216 1216 periods o...

Page 1082: ...CHER Address 0x4003C010 Access Write only This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register CHx Channel x Enable 0 No effect 1 Enables the corresponding channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1 CH0 ...

Page 1083: ...C Write Protect Mode Register CHx Channel x Disable 0 No effect 1 Disables the corresponding channel Warning If the corresponding channel is disabled during a conversion or if it is disabled then re enabled during a conver sion its associated analog value and its corresponding EOC flags in DACC_ISR are unpredictable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 1084: ...CC Channel Status Register Name DACC_CHSR Address 0x4003C018 Access Read only CHx Channel x Status 0 Corresponding channel is disabled 1 Corresponding channel is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1 CH0 ...

Page 1085: ...ACC_CDR Address 0x4003C020 Access Write only DATA Data to Convert When the WORD bit in DACC_MR register is cleared only DATA 15 0 is used else DATA 31 0 is used to write 2 data to be converted 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA ...

Page 1086: ...ess 0x4003C024 Access Write only TXRDY Transmit Ready Interrupt Enable EOC End of Conversion Interrupt Enable ENDTX End of Transmit Buffer Interrupt Enable TXBUFE Transmit Buffer Empty Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBUFE ENDTX EOC TXRDY ...

Page 1087: ...ss 0x4003C028 Access Write only TXRDY Transmit Ready Interrupt Disable EOC End of Conversion Interrupt Disable ENDTX End of Transmit Buffer Interrupt Disable TXBUFE Transmit Buffer Empty Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBUFE ENDTX EOC TXRDY ...

Page 1088: ...Address 0x4003C02C Access Read only TXRDY Transmit Ready Interrupt Mask EOC End of Conversion Interrupt Mask ENDTX End of Transmit Buffer Interrupt Mask TXBUFE Transmit Buffer Empty Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBUFE ENDTX EOC TXRDY ...

Page 1089: ...version has been performed since the last DACC_ISR read ENDTX End of DMA Interrupt Flag 0 The Transmit Counter Register has not reached 0 since the last write in DACC_TCR or DACC_TNCR 1 The Transmit Counter Register has reached 0 since the last write in DACC _TCR or DACC_TNCR TXBUFE Transmit Buffer Empty 0 The Transmit Counter Register has not reached 0 since the last write in DACC_TCR or DACC_TNC...

Page 1090: ...ter IBCTLCHx Analog Output Current Control Allows to adapt the slew rate of the analog output See the product electrical characteristics for further details IBCTLDACCORE Bias Current Control for DAC Core Allows to adapt performance versus power consumption See the product electrical characteristics for further details 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 IBCTLDACCO...

Page 1091: ...ect if WPKEY corresponds to 0x444143 DAC in ASCII The protected registers are DACC Mode Register DACC Channel Enable Register DACC Channel Disable Register DACC Analog Current Register WPKEY Write Protect KEY This security code is needed to set reset the WPROT bit value see Section 41 6 8 Write Protection Registers for details Must be filled with DAC ASCII code 31 30 29 28 27 26 25 24 WPKEY 23 22 ...

Page 1092: ... 0x4003C0E8 Access Read only WPROTADDR Write protection error address Indicates the address of the register write request which generated the error WPROTERR Write protection error Indicates a write protection error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WPROTADDR 7 6 5 4 3 2 1 0 WPROTERR ...

Page 1093: ... operation of the device at these or other conditions beyond those indi cated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Storage Temperature 60 C to 150 C Voltage on Input Pins with Respect to Ground 0 3V to 4 0V Maximum Operating Voltage VDDCORE 1 32V Maximum Operating Voltage V...

Page 1094: ... VOH Output High level Voltage PA0 PA31 PB0 PB9 PB12 PB14 PC0 PC31 IOL 4 0 mA VVDDIO 0 4V V VDDIO 3 0V 3 60V PB10 PB11 VVDDIO 0 15V VOL Output Low level Voltage PA0 PA31 PB0 PB9 PB12 PB14 PC0 PC31 IOH 4 0 mA 0 4 V VDDIO 3 0V 3 60V PB10 PB11 0 15 VHys Hysteresis Voltage PA0 PA31 PB0 PB9 PB12 PB14 PC0 PC31 Hysteresis mode enabled 150 mV IO IOH or ISOURCE VDDIO 1 65V 3 60V VOH VVDDIO 0 4V PA14 SPCK P...

Page 1095: ...below to VDDIN voltage 0 5V IIH Input High Pull_down OFF 1 1 µA Pull_down ON 10 50 RPULLUP Pull up Resistor PA0 PA31 PB0 PB14 PC0 PC31 NRST 70 100 130 kΩ RPULLDOWN Pull down Resistor PA0 PA31 PB0 PB14 PC0 PC31 NRST 70 100 130 kΩ RODT On die Series Termination Resistor PA4 PA31 PB0 PB9 PB12 PB14 PC0 PC31 PA0 PA3 36 18 Ω Table 42 2 DC Characteristics Continued Symbol Parameter Conditions Min Typ Max...

Page 1096: ...elow to VDDIN voltage 0 5V Table 42 3 1 2V Voltage Regulator Characteristics Symbol Parameter Conditions Min Typ Max Units VVDDIN DC Input Voltage Range 4 5 1 6 3 3 3 6 V VVDDOUT DC Output Voltage Normal Mode Standby Mode 1 2 0 V VACCURACY Output Voltage Accuracy ILoad 0 8mA to 80 mA after trimming 3 3 ILOAD ILOAD START Maximum DC Output Current Maximum Peak Current during startup VVDDIN 1 8V VVDD...

Page 1097: ...etector disabled 24 2 µA µA IDD33ON IDD33OFF Current Consumption on VDDIO Brownout Detector enabled Brownout Detector disabled 24 2 µA µA Td VTH detection propagation time VDDCORE VTH to VTH 100mV 200 300 ns TSTART Startup Time From disabled state to enabled state 300 µs t VDDCORE Vth Vth BOD OUTPUT t td td Table 42 5 VDDIO Supply Monitor Symbol Parameter Conditions Min Typ Max Units VTH Supply Mo...

Page 1098: ...yp V Threshold max V 0000 1 58 1 6 1 62 0001 1 7 1 72 1 74 0010 1 82 1 84 1 86 0011 1 94 1 96 1 98 0100 2 05 2 08 2 11 0101 2 17 2 2 2 23 0110 2 29 2 32 2 35 0111 2 41 2 44 2 47 1000 2 53 2 56 2 59 1001 2 65 2 68 2 71 1010 2 77 2 8 2 83 1011 2 8 2 92 2 95 1100 3 0 3 04 3 07 1101 3 12 3 16 3 2 1110 3 24 3 28 3 32 1111 3 36 3 4 3 44 Vth Vhyst VDDIO Reset Vth ...

Page 1099: ...g At Startup 1 45 1 53 1 59 V Vth Threshold voltage falling 1 35 1 45 1 55 V Tres Reset Time out Period 100 240 500 µs Vth Vth VDDIO Reset Table 42 8 DC Flash Characteristics Symbol Parameter Conditions Typ Max Units ICC Active current Random 144 bit Read Maximum Read Frequency onto VDDCORE 1 2V 25 C 16 25 mA Random 72 bit Read Maximum Read Frequency onto VDDCORE 1 2V 25 C 10 18 mA Program onto VD...

Page 1100: ... then disabled the corresponding clock 42 3 1 Backup Mode Current Consumption The Backup Mode configuration and measurements are defined as follows Figure 42 4 Measurement Setup 42 3 1 1 Configuration A Supply Monitor on VDDIO is disabled RTT and RTC not used Embedded slow clock RC Oscillator used One WKUPx enabled Current measurement on AMP1 See Figure 42 4 42 3 1 2 Configuration B Supply Monitor...

Page 1101: ... consumption in typical conditions Table 42 9 Power Consumption for Backup Mode Configuration A and B Conditions Total Consumption AMP1 Configuration A Total Consumption AMP1 Configuration B Unit VDDIO 3 3V 25 C VDDIO 3 0V 25 C VDDIO 2 5V 25 C VDDIO 1 8V 25 C 1 98 1 79 1 51 1 1 85 1 66 1 37 0 95 µA VDDIO 3 3V 85 C VDDIO 3 0V 85 C VDDIO 2 5V 85 C VDDIO 1 8V 85 C 13 0 12 0 10 5 8 78 12 42 11 42 10 0...

Page 1102: ... with PLLA Core Clock MCK MHz VDDCORE Consumption AMP1 Total Consumption AMP2 Unit 120 8 1 9 9 mA 100 6 7 8 3 mA 84 5 7 7 1 mA 64 4 5 6 4 mA 48 3 4 4 8 mA 32 2 3 3 38 mA 24 1 8 3 31 mA 0 000 2 000 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 Processor and Peripheral Clocks in MHz VDDCORE IDDCORE in mA 0 000 2 000 4 000 6 000 8 000 0 10 20 30 40 50 60 70 80 90 100 110 120 Processor and Periphera...

Page 1103: ...ation Running from Flash Memory with128 bit access Mode All Peripheral clocks are deactivated Master Clock MCK running at various frequencies with PLLA or the fast RC oscillator Current measurement on AMP1 VDDCORE and total current on AMP2 Table 42 12 Typical Current Consumption in Wait Mode Conditions VDDOUT Consumption AMP1 Total Consumption AMP2 Unit See Figure 42 7 on page 1103 25 C There is n...

Page 1104: ...wer Consumption with VDDCORE 1 2V running from Flash Memory or SRAM Core Clock MHz CoreMark Unit 128 bit Flash access 1 64 bit Flash access 1 AMP1 AMP2 AMP1 AMP2 mA 120 24 9 28 8 18 21 4 100 21 9 25 4 16 3 19 5 84 18 5 21 4 13 8 16 6 64 15 0 17 6 11 4 13 9 48 11 9 14 3 9 6 11 8 32 8 1 9 9 7 4 9 3 24 6 0 7 7 5 8 7 5 12 3 4 6 1 3 2 6 0 8 2 3 4 5 2 2 4 5 4 1 2 2 6 1 2 2 9 2 0 7 1 9 0 7 2 0 1 0 4 1 3 ...

Page 1105: ...1105 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...

Page 1106: ...O 3 3V VDDCORE 1 08V TA 25 C Table 42 14 Power Consumption on VDDCORE 1 Peripheral Consumption Typ Unit PIO Controller A PIOA 5 6 µA MHz PIO Controller B PIOB 7 5 PIO Controller C PIOC 5 9 UART 3 8 USART 7 7 PWM 10 5 TWI 5 8 SPI 6 9 Timer Counter TCx 4 7 ADC 5 2 DACC 5 2 ACC 1 3 HSMCI 7 7 CRCCU 1 4 SMC 3 6 SSC 6 1 UDP 5 ...

Page 1107: ...mperature Dependency Over temperature range 40 C 85 C versus 25 C 7 7 Duty Duty Cycle 45 50 55 TON Startup Time 100 µs IDDON Current Consumption After Startup Time Temp Range 40 C to 125 C Typical Consumption at 2 2V supply and Temp 25 C 540 860 nA Table 42 16 4 8 12 MHz RC Oscillators Characteristics Symbol Parameter Conditions Min Typ Max Unit FRange RC Oscillator Frequency Range 1 4 12 MHz ACC4...

Page 1108: ...30 mV Duty Cycle 40 50 60 Startup Time Rs 50KΩ Rs 100KΩ 1 Ccrystal 12 5pF Ccrystal 6pF Ccrystal 12 5pF Ccrystal 6pF 900 300 1200 500 ms Iddon Current consumption Rs 50KΩ Rs 100KΩ 1 Ccrystal 12 5pF Ccrystal 6pF Ccrystal 12 5pF Ccrystal 6pF 550 380 820 530 1150 980 1600 1350 nA PON Drive level 0 1 µW Rf Internal resistor between XIN32 and XOUT32 10 MΩ CLEXT Maximum external capacitor on XIN32 and XO...

Page 1109: ...l Parameter Conditions Min Typ Max Unit Freq Operating Frequency Normal mode with crystal 3 16 20 MHz Supply Ripple Voltage on VDDPLL Rms value 10 KHz to 10 MHz 30 mV Duty Cycle 40 50 60 TON Startup Time 3 MHz CSHUNT 3pF 8 MHz CSHUNT 7pF 16 MHz CSHUNT 7pF with Cm 8fF 16 MHz CSHUNT 7pF with Cm 1 6fF 20 MHz CSHUNT 7pF 14 5 4 1 4 2 5 1 ms IDD_ON Current consumption on VDDIO 3 MHz 2 8 MHz 3 16 MHz 4 2...

Page 1110: ...ift Drive Level Crystal drive level Oscillator Drive Level Having a crystal drive level number lower than the oscillator specification may damage the crystal Equivalent Series Resistor ESR Crystal ESR Oscillator ESR Max Having a crystal with ESR value higher than the oscillator may cause the oscillator to not start Shunt Capacitance Max crystal Shunt capacitance Oscillator Shunt Capacitance CSHUNT...

Page 1111: ...2 1 32 V Allowable Voltage Ripple RMS Value 10 kHz to 10 MHz RMS Value 10 MHz 20 10 mV Table 42 22 PLLA and PLLB Characteristics Symbol Parameter Conditions Min Typ Max Unit FIN Input Frequency 3 32 MHz FOUT Output Frequency 80 240 MHz IPLL Current Consumption Active mode 80 MHz 1 2V Active mode 96 MHz 1 2V Active mode 160 MHz 1 2V Active Mode 240 MHz 1 2V 0 94 1 2 2 1 3 34 1 2 1 5 2 5 4 mA TSTART...

Page 1112: ...tate Data Line Leakage 0V VIN 3 3V 10 10 µA REXT Recommended External USB Series Resistor In series with each USB pin with 5 27 Ω Output Levels VOL Low Level Output Measured with RL of 1 425 kΩ tied to 3 6V 0 0 0 3 V VOH High Level Output Measured with RL of 14 25 kΩ tied to GND 2 8 3 6 V VCRS Output Signal Crossover Voltage Measure conditions described in Figure 42 9 USB Data Signal Rise and Fall...

Page 1113: ... Fall Times Table 42 24 In Full Speed Symbol Parameter Conditions Min Typ Max Unit tFR Transition Rise Time CLOAD 50 pF 4 20 ns tFE Transition Fall Time CLOAD 50 pF 4 20 ns tFRFM Rise Fall time Matching 90 111 11 10 10 90 VCRS tR tF Differential Data Lines Rise Time Fall Time Fosc 6MHz 750kHz REXT 27 ohms Cload Buffer b a ...

Page 1114: ...Parameter Conditions Min Typ Max Units fADC ADC Clock Frequency 1 20 MHz tCP_ADC ADC Clock Period 50 1000 ns fS Sampling Frequency 1 MHz tSTART UP ADC Startup time From OFF Mode to Normal Mode Voltage Reference OFF Analog Circuitry OFF From Standby Mode to Normal Mode Voltage Reference ON Analog Circuitry OFF 20 4 30 8 40 12 µs tTRACKTIM Track and Hold Time See Section 42 7 1 1 Track and Hold Time...

Page 1115: ... Max Units Resolution 12 Bit Integral Non linearity INL Differential mode or single mode Gain xx 4 1 4 LSB Differential Non linearity DNL Differential mode or single mode Gain xx 2 0 5 2 LSB Table 42 29 Gain and Error offset 12 bit Mode VDDIN 2 4V to 3 6V supply voltage conditions Parameter Conditions Min Typ Max Units Offset Error Differential mode Gain xx 24 8 24 LSB Single Ended Gain 1 16 5 16 ...

Page 1116: ...nditions Min Typ Max Units Resolution 10 Bit Integral Non linearity INL 0 5 1 LSB Differential Non linearity DNL No missing code 0 5 1 LSB Offset Error 10 10 LSB Gain Error 7 7 LSB Table 42 31 Dynamic Performance Characteristics in Single ended and 12 bits mode 1 Parameter Conditions Min Typ Max Units Signal to Noise Ratio SNR 58 64 72 dB Total Harmonic Distortion THD 84 74 66 dB Signal to Noise a...

Page 1117: ...king time tTRACK is higher than 15 tCP_ADC Set TRANSFER 1 and TRACTIM 0 In this case a timer will trigger the ADC in order to set the correct sampling rate according to the Track time The maximum possible sampling frequency will be defined by tTRACK in nano seconds computed by the previous formula but with minus 15 tCP_ADC and plus TRANSFER time 10 bit mode 1 fS tTRACK 15 tCP_ADC 5 tCP_ADC 12 bit ...

Page 1118: ...6 V Max Voltage Ripple rms value 10 kHz to 20 MHz 20 mV IVDDIN Current Consumption Sleep Mode Clock OFF Fast Wake Up Standby Mode Clock on Normal Mode with 1 Output On IBCTLDACCORE 01 IBCTLCHx 10 Normal Mode with 2 Outputs On IBCTLDACCORE 01 IBCTLCHx 10 2 4 3 5 3 3 5 6 6 5 µA mA mA mA Table 42 35 Channel Conversion Time and DAC Clock Symbol Parameter Conditions Min Typ Max Units FDAC Clock Frequen...

Page 1119: ...olution 12 Bit Integral Non linearity INL 2 4V VVDDIN 2 7V 2 7V VVDDIN 3 6V 6 2 1 6 2 LSB Differential Non linearity DNL 2 4V VVDDIN 2 7V 2 7V VVDDIN 3 6V 2 5 1 2 5 LSB Offset Error 32 8 32 LSB Gain Error 32 2 32 LSB Table 42 37 Dynamic Performance Characteristics Parameter Conditions Min Typ Max Units Signal to Noise Ratio SNR 2 4V VVDDIN 2 7V 2 7V VVDDIN 3 6V 50 62 62 70 70 74 dB Total Harmonic ...

Page 1120: ...e load IBCTLCHx 00 IBCTLCHx 01 IBCTLCHx 10 IBCTLCHx 11 0 23 0 45 0 67 0 89 mA Settling Time RLOAD 10kΩ 0pF CLOAD 50pF 0 5 µs RLOAD Output Load Resistor 10 kΩ CLOAD Output Load Capacitor 30 50 pF Analog Comparator Characteristics Parameter Conditions Min Typ Max Units Voltage Range The Analog Comparator is supplied by VDDIN 1 62 3 3 3 6 V Input Voltage Range GND 0 2 VDDIN 0 2 V Input Offset Voltage...

Page 1121: ...to define the maximum frequency of the I Os Output duty cycle 40 60 Minimum output swing 100 mV to VDDIO 100 mV Minimum output swing 100 mV to VDDIO 100 mV Addition of rising and falling time inferior to 75 of the period Table 42 39 Temperature Sensor Characteristics Symbol Parameter Conditions Min Typ Max Units VT Output Voltage T 27 C 1 44 V ΔVT Output Voltage Accuracy T 27 C 50 50 mV dVT dT Tem...

Page 1122: ...6 MHz 25 pF VDDIO 1 62V 23 PulseminH2 Pin Group 2 2 High Level Pulse Width 10 pF VDDIO 1 62V 11 ns 25pF VDDIO 1 62V 21 8 PulseminL2 Pin Group 2 2 Low Level Pulse Width 10 pF VDDIO 1 62V 11 ns 25 pF VDDIO 1 62V 21 8 FreqMax3 Pin Group3 3 Maximum output frequency 10 pF VDDIO 1 62V 70 MHz 25 pF VDDIO 1 62V 35 PulseminH3 Pin Group 3 3 High Level Pulse Width 10 pF VDDIO 1 62V 7 2 ns 25 pF VDDIO 1 62V 1...

Page 1123: ...aster Mode with CPOL NCPHA 0 or CPOL NCPHA 1 Figure 42 12 SPI Master Mode with CPOL 0 and NCPHA 1 or CPOL 1 and NCPHA 0 Figure 42 13 SPI Slave Mode with CPOL 0 and NCPHA 1 or CPOL 1 and NCPHA 0 SPCK MISO MOSI SPI2 SPI0 SPI1 SPCK MISO MOSI SPI5 SPI3 SPI4 SPCK MISO MOSI SPI6 SPI7 SPI8 NPCSS SPI12 SPI13 ...

Page 1124: ... the one from the pad Master Read Mode Tvalid is the slave time response to output data after detecting an SPCK edge For Atmel SPI DataFlash AT45DB642D Tvalid or Tv is 12 ns Max In the formula above FSPCKMax 33 0 MHz VDDIO 3 3V Slave Read Mode In slave mode SPCK is the input clock for the SPI The max SPCK frequency is given by setup and hold timings SPI7 SPI8 or SPI10 SPI11 Since this gives a freq...

Page 1125: ...main 2 18 4 ns SPI4 MISO Hold time after SPCK falls master 3 3V domain 1 0 ns 1 8V domain 2 0 ns SPI5 SPCK falling to MOSI Delay master 3 3V domain 1 7 3 6 ns 1 8V domain 2 6 7 4 2 ns SPI6 SPCK falling to MISO Delay slave 3 3V domain 1 3 4 11 1 ns 1 8V domain 2 4 1 13 1 ns SPI7 MOSI Setup time before SPCK rises slave 3 3V domain 1 0 ns 1 8V domain 2 0 ns SPI8 MOSI Hold time after SPCK rises slave ...

Page 1126: ... the SDIO V2 0 specification and CE ATA V1 1 42 11 5 SSC Timings Timings are given in the following domain 1 8V domain VDDIO from 1 65V to 1 95V maximum external capacitor 20 pF 3 3V domain VDDIO from 2 85V to 3 6V maximum external capacitor 30 pF Figure 42 15 SSC Transmitter TK and TF as output Figure 42 16 SSC Transmitter TK as input and TF as output TK CKI 1 TF TD SSC0 TK CKI 0 TK CKI 1 TF TD S...

Page 1127: ...re 42 17 SSC Transmitter TK as output and TF as input Figure 42 18 SSC Transmitter TK and TF as input Figure 42 19 SSC Receiver RK and RF as input TK CKI 1 TF SSC2 SSC3 TK CKI 0 TD SSC4 TK CKI 0 TF SSC5 SSC6 TK CKI 1 TD SSC7 RK CKI 1 RF RD SSC8 SSC9 RK CKI 0 ...

Page 1128: ... 20 SSC Receiver RK as input and RF as output Figure 42 21 SSC Receiver RK and RF as output Figure 42 22 SSC Receiver RK as output and RF as input RK CKI 0 RD SSC8 SSC9 RK CKI 1 RF SSC10 RK CKI 0 RD SSC11 SSC12 RK CKI 1 RF SSC13 RK CKI 1 RF RD SSC11 SSC12 RK CKI 0 ...

Page 1129: ...main 3 3 3v domain 4 4 5 3 8 16 3 13 3 ns SSC2 TF setup time before TK edge TK output 1 8v domain 3 3 3v domain 4 14 8 12 0 ns SSC3 TF hold time after TK edge TK output 1 8v domain 3 3 3v domain 4 0 ns SSC4 1 TK edge to TF TD TK output TF input 1 8v domain 3 3 3v domain 4 2 6 2 tCPMCK 1 4 2 3 2 tCPMCK 1 4 5 4 2 tCPMCK 1 4 5 0 2 tCPMCK 1 4 ns SSC5 TF setup time before TK edge TK input 1 8v domain 3...

Page 1130: ...min TK CKI 1 SSC0max Table 42 44 SMC Read Signals NRD Controlled READ_MODE 1 Symbol Parameter Min Max Units VDDIO Supply 1 8V 2 3 3V 3 1 8V 2 3 3V 3 NO HOLD SETTINGS nrd hold 0 SMC1 Data Setup before NRD High 19 9 17 9 ns SMC2 Data Hold after NRD High 0 0 ns HOLD SETTINGS nrd hold 0 SMC3 Data Setup before NRD High 16 0 14 0 ns SMC4 Data Hold after NRD High 0 0 ns HOLD or NO HOLD SETTINGS nrd hold ...

Page 1131: ...d setup ncs rd pulse tCPMCK 6 3 ns SMC13 NRD low before NCS High ncs rd setup ncs rd pulse nrd setup tCPMCK 5 6 ncs rd setup ncs rd pulse nrd setup tCPMCK 5 4 ns SMC14 NCS Pulse Width ncs rd pulse length tCPMCK 7 7 ncs rd pulse length tCPMCK 6 7 ns Table 42 46 SMC Write Signals NWE Controlled WRITE_MODE 1 Symbol Parameter Min Max Units 1 8V 2 3 3V 3 1 8V 2 3 3V 3 HOLD or NO HOLD SETTINGS nwe hold ...

Page 1132: ...2 A1 NBS3 A2 A25 NCS change 1 3 0 2 8 ns Table 42 46 SMC Write Signals NWE Controlled WRITE_MODE 1 Continued Symbol Parameter Min Max Units 1 8V 2 3 3V 3 1 8V 2 3 3V 3 Table 42 47 SMC Write NCS Controlled WRITE_MODE 0 Symbol Parameter Min Max Units 1 8V 2 3 3V 3 1 8V 2 3 3V 3 SMC22 Data Out Valid before NCS High ncs wr pulse tCPMCK 6 3 ncs wr pulse tCPMCK 6 2 ns SMC23 NCS Pulse Width ncs wr pulse ...

Page 1133: ...trolled READ with HOLD NCS Controlled WRITE SMC22 SMC26 SMC10 SMC11 SMC12 SMC9 SMC8 SMC14 SMC14 SMC23 SMC27 SMC26 A0 A23 SMC24 SMC25 SMC12 SMC13 SMC13 NRD NCS DATA NWE A0 A23 NRD Controlled READ with NO HOLD NWE Controlled WRITE with NO HOLD NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD SMC1 SMC2 SMC15 SMC21 SMC3 SMC4 SMC15 SMC19 SMC20 SMC7 SMC21 SMC16 SMC7 SMC16 SMC19 SMC21 SMC17 S...

Page 1134: ...de Figure 42 27 USART SPI Slave Mode Mode 1 or 2 NSS SPI0 MSB LSB SPI1 CPOL 1 CPOL 0 MISO MOSI SCK SPI5 SPI2 SPI3 SPI4 SPI4 the MOSI line is driven by the output pin TXD the MISO line drives the input pin RXD the SCK line is driven by the output pin SCK the NSS line is driven by the output pin RTS SCK MISO MOSI SPI6 SPI7 SPI8 NSS SPI12 SPI13 the MOSI line drives the input pin RXD the MISO line is ...

Page 1135: ...5 MCK 1 0 ns SPI2 Input Data Hold Time 1 8v domain 3 3v domain 1 5 MCK 0 3 1 5 MCK 0 1 ns SPI3 Chip Select Active to Serial Clock 1 8v domain 3 3v domain 1 5 SPCK 1 5 1 5 SPCK 2 1 ns SPI4 Output Data Setup Time 1 8v domain 3 3v domain 7 9 7 2 9 9 10 7 ns SPI5 Serial Clock to Chip Select Inactive 1 8v domain 3 3v domain 1 SPCK 4 1 1 SPCK 4 8 ns Slave Mode SPI6 SCK falling to MISO 1 8V domain 3 3V d...

Page 1136: ...domain 3 3v domain 2 MCK 0 7 2 MCK 0 6 ns SPI11 MOSI Hold time after SCK falls 1 8v domain 3 3v domain 0 2 0 1 ns SPI12 NPCS0 setup to SCK rising 1 8v domain 3 3v domain 2 5 MCK 0 5 2 5 MCK ns SPI13 NPCS0 hold after SCK falling 1 8v domain 3 3v domain 1 5 MCK 0 2 1 5 MCK ns SPI14 NPCS0 setup to SCK falling 1 8v domain 3 3v domain 2 5 MCK 0 5 2 5 MCK 0 3 ns SPI15 NPCS0 hold after SCK rising 1 8v do...

Page 1137: ...m VIHmin to VILmax 10 pF Cb 400 pF Figure 42 29 20 0 1Cb 1 2 250 ns Ci 1 Capacitance for each I O Pin 10 pF fTWCK TWCK Clock Frequency 0 400 kHz Rp Value of Pull up resistor fTWCK 100 kHz Ω fTWCK 100 kHz Ω tLOW Low Period of the TWCK clock fTWCK 100 kHz 3 µs fTWCK 100 kHz 3 µs tHIGH High period of the TWCK clock fTWCK 100 kHz 4 µs fTWCK 100 kHz 4 µs tHD STA Hold Time repeated START Condition fTWCK...

Page 1138: ...y The embedded flash is fully tested during production test the flash contents are not set to a known state prior to shipment Therefore the flash contents should be erased prior to programming an application Table 42 50 Embedded Flash Wait State VDDCORE set at 1 08V and VDDIO 1 62V to 3 6V 85C FWS Read Operations Maximum Operating Frequency MHz 0 1 cycle 16 1 2 cycles 33 2 3 cycles 50 3 4 cycles 6...

Page 1139: ...2 7V to 3 6V 85C FWS Read Operations Maximum Operating Frequency MHz 0 1 cycle 21 1 2 cycles 42 2 3 cycles 63 3 4 cycles 84 4 5 cycles 105 5 6 cycles 123 Table 42 54 AC Flash Characteristics Parameter Conditions Min Typ Max Units Program Cycle Time Erase page mode 10 50 ms Erase block mode by 4Kbytes 50 200 ms Erase sector mode 400 950 ms Full Chip Erase 1 MBytes 512 KBytes 9 5 5 18 11 s Data Rete...

Page 1140: ... Drawing Note 1 This drawing is for general information only Refer to JEDEC Drawing MS 026 for additional information Table 43 1 Device and LQFP Package Maximum Weight SAM4S 800 mg Table 43 2 Package Reference JEDEC Drawing Reference MS 026 JESD97 Classification e3 Table 43 3 LQFP Package Characteristics Moisture Sensitivity Level 3 ...

Page 1141: ...re 43 2 100 ball TFBGA Package Drawing Table 43 4 Soldering Information Substrate Level Ball Land TBD Soldering Mask Opening TBD Table 43 5 Device Maximum Weight TBD mg Table 43 6 100 ball Package Characteristics Moisture Sensitivity Level 3 Table 43 7 Package Reference JEDEC Drawing Reference TBD JESD97 Classification e1 ...

Page 1142: ...1142 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 3 100 ball VFBGA Package Drawing ...

Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...

Page 1144: ... 003 0 008 R1 0 08 0 003 θ 0 3 5 7 0 3 5 7 θ1 0 0 θ2 11 12 13 11 12 13 θ3 11 12 13 11 12 13 c 0 09 0 20 0 004 0 008 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 REF 0 039 REF S 0 20 0 008 b 0 17 0 20 0 27 0 007 0 008 0 011 e 0 50 BSC 0 020 BSC D2 7 50 0 285 E2 7 50 0 285 Tolerances of Form and Position aaa 0 20 0 008 bbb 0 20 0 008 ccc 0 08 0 003 ddd 0 08 0 003 Table 43 9 Device and LQFP Package Max...

Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...

Page 1146: ...9 0 010 0 011 D 9 00 bsc 0 354 bsc D2 6 95 7 10 7 25 0 274 0 280 0 285 E 9 00 bsc 0 354 bsc E2 6 95 7 10 7 25 0 274 0 280 0 285 L 0 35 0 40 0 45 0 014 0 016 0 018 e 0 50 bsc 0 020 bsc R 0 125 0 0005 Tolerances of Form and Position aaa 0 10 0 004 bbb 0 10 0 004 ccc 0 05 0 002 Table 43 13 Device and QFN Package Maximum Weight Preliminary SAM4S 280 mg Table 43 14 QFN Package Reference JEDEC Drawing R...

Page 1147: ...1A and IPC 782 Generic Requirements for Surface Mount Design and Land Pattern Standards http landpatterns ipc org default asp Atmel Green and RoHS Policy and Package Material Declaration Data Sheet http www atmel com green Table 43 16 Soldering Profile Profile Feature Green Package Average Ramp up Rate 217 C to Peak 3 C sec max Preheat Temperature 175 C 25 C 180 sec max Temperature Maintained Abov...

Page 1148: ... ATARM 31 Jul 12 SAM4S Series Preliminary 44 SAM4S Series Errata Please refer to the dedicated documents Errata on SAM4S8 S16 Engineering Sample Devices and Errata on SAM4SA16 SD16 SD32 Engineering Sample Devices ...

Page 1149: ...reen Industrial 40 C to 85 C ATSAM4SD16CA AU A 2 512 LQFP100 Green Industrial 40 C to 85 C ATSAM4SD16BA MU A 2 512 QFN64 Green Industrial 40 C to 85 C ATSAM4SD16BA AU A 2 512 LQFP64 Green Industrial 40 C to 85 C ATSAM4SA16CA CU A 1024 TFBGA100 Green Industrial 40 C to 85 C ATSAM4SA16CA CFU A 1024 VFBGA100 Green Industrial 40 C to 85 C ATSAM4SA16CA AU A 1024 LQFP100 Green Industrial 40 C to 85 C AT...

Page 1150: ... VFBGA100 Green Industrial 40 C to 85 C ATSAM4S8CA AU A 512 LQFP100 Green Industrial 40 C to 85 C ATSAM4S8BA MU A 512 QFN64 Green Industrial 40 C to 85 C ATSAM4S8BA AU A 512 LQFP64 Green Industrial 40 C to 85 C Table 45 1 Ordering Codes for SAM4S Devices Ordering Code MRL Flash Kbytes Package Package Type Temperature Operating Range ...

Page 1151: ... 1 on page 26 SRAM upper address changed to 0x20400000 and EFC1 added in Figure 7 1 on page 29 Note added in Section 8 1 3 1 Flash Overview on page 30 New devices features added in Section 8 1 1 Internal SRAM on page 30 Section 8 1 3 1 Flash Overview on page 30 Section 8 1 3 4 Lock Regions on page 34 Section 8 1 3 5 Security Bit Feature on page 34 Section 8 1 3 11 GPNVM Bits on page 35 EEFC replac...

Page 1152: ... from 0x400E0800 to 0x400E0A00 in Section 19 5 Enhanced Embedded Flash Controller EEFC User Interface on page 340 8076 8274 rfo FFPI All references tables figures related to 48 bit devices cleared in this whole chapter rfo CMCC New chapter CRCCU Typos CCIT802 corrected to CCITT802 CCIT16 corrected to CCITT16 in Section 22 5 1 CRC Calculation Unit description on page 371 and Section 22 7 10 CRCCU M...

Page 1153: ...he ADREF Current row from Table 42 27 on page 1114 Updated the Offset Error parameter description in Table 42 29 on page 1115 Updated the TACCURACY parameter description in Table 42 5 on page 1097 Updated the temperature sensor description in Section 42 10 Temperature Sensor and the slope accuracy parameter data in Table 42 39 on page 1121 8085 8245 8223 rfo rfo rfo Mechanical Characteristics 48 p...

Page 1154: ...5 1 Power Supplies 19 5 2 Voltage Regulator 19 5 3 Typical Powering Schematics 19 5 4 Active Mode 21 5 5 Low power Modes 21 5 6 Wake up Sources 24 5 7 Fast Startup 25 6 Input Output Lines 26 6 1 General Purpose I O Lines 26 6 2 System I O Lines 26 6 3 Test Pin 28 6 4 NRST Pin 28 6 5 ERASE Pin 28 7 Product Mapping 29 8 Memories 30 8 1 Embedded Memories 30 8 2 External Memories 36 9 System Controlle...

Page 1155: ...er SysTick 220 11 11 Memory Protection Unit MPU 225 11 12 Glossary 239 12 Debug and Test Features 243 12 1 Description 243 12 2 Embedded Characteristics 243 12 3 Application Examples 244 12 4 Debug and Test Pin Description 245 12 5 Functional Description 246 13 Reset Controller RSTC 251 13 1 Description 251 13 2 Embedded Characteristics 251 13 3 Block Diagram 251 13 4 Functional Description 252 13...

Page 1156: ...7 3 Block Diagram 304 17 4 Supply Controller Functional Description 305 17 5 Supply Controller SUPC User Interface 314 18 General Purpose Backup Registers GPBR 323 18 1 Description 323 18 2 Embedded Characteristics 323 18 3 General Purpose Backup Registers GPBR User Interface 323 19 Enhanced Embedded Flash Controller EEFC 325 19 1 Description 325 19 2 Embedded Characteristics 325 19 3 Product Depe...

Page 1157: ... Interface 377 23 SAM4S Boot Program 393 23 1 Description 393 23 2 Hardware and Software Constraints 393 23 3 Flow Diagram 393 23 4 Device Initialization 394 23 5 SAM BA Monitor 395 24 Bus Matrix MATRIX 399 24 1 Description 399 24 2 Embedded Characteristics 399 24 3 Memory Mapping 400 24 4 Special Bus Granting Techniques 400 24 5 Arbitration 401 24 6 System I O Configuration 403 24 7 Write Protect...

Page 1158: ...ontroller PDC User Interface 464 27 Power Management Controller PMC 475 27 1 Clock Generator 475 27 2 Power Management Controller PMC 483 28 Chip Identifier CHIPID 527 28 1 Description 527 28 2 Embedded Characteristics 527 28 3 Chip Identifier CHIPID User Interface 529 29 Parallel Input Output Controller PIO 535 29 1 Description 535 29 2 Embedded Characteristics 535 29 3 Block Diagram 536 29 4 Pro...

Page 1159: ...PI User Interface 651 32 Two wire Interface TWI 667 32 1 Description 667 32 2 Embedded Characteristics 667 32 3 List of Abbreviations 668 32 4 Block Diagram 668 32 5 Application Block Diagram 669 32 6 Product Dependencies 670 32 7 Functional Description 671 32 8 Master Mode 672 32 9 Multi master Mode 684 32 10 Slave Mode 687 32 11 Two wire Interface TWI User Interface 695 33 Universal Asynchronous...

Page 1160: ...07 35 6 Functional Description 808 35 7 Timer Counter TC User Interface 832 36 High Speed Multimedia Card Interface HSMCI 859 36 1 Description 859 36 2 Embedded Characteristics 859 36 3 Block Diagram 860 36 4 Application Block Diagram 861 36 5 Pin Name List 861 36 6 Product Dependencies 862 36 7 Bus Topology 862 36 8 High Speed MultiMediaCard Operations 865 36 9 SD SDIO Card Operation 873 36 10 CE...

Page 1161: ...troller ACC 1017 39 1 Description 1017 39 2 Embedded Characteristics 1017 39 3 Block Diagram 1018 39 4 Pin Name List 1019 39 5 Product Dependencies 1020 39 6 Functional Description 1021 39 7 Analog Comparator Controller ACC User Interface 1022 40 Analog to Digital Converter ADC 1033 40 1 Description 1033 40 2 Embedded Characteristics 1033 40 3 Block Diagram 1034 40 4 Signal Description 1034 40 5 P...

Page 1162: ...2 4 Oscillator Characteristics 1107 42 5 PLLA PLLB Characteristics 1111 42 6 USB Transceiver Characteristics 1112 42 7 12 Bit ADC Characteristics 1114 42 8 12 Bit DAC Characteristics 1118 42 9 Analog Comparator Characteristics 1120 42 10 Temperature Sensor 1121 42 11 AC Characteristics 1121 43 SAM4S Mechanical Characteristics 1140 43 1 Soldering Profile 1147 43 2 Packaging Resources 1147 44 SAM4S ...

Page 1163: ...HANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE...

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Atmel SAM4S Series, Preliminary Data Sheet

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