Atmel SAM4S Series, Preliminary Data Sheet

Page: 920 / 1163

920
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Update Period Register” (PWM_SCUP) (see “Method 2: Manual write of duty-cycle values
and automatic trigger of the update” on page 921 ).
• Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of
ALL synchronous channels are written by the Peripheral DMA Controller (PDC) (see “Method
3: Automatic write of duty-cycle values and automatic trigger of the update” on page 923 ).
The user can choose to synchronize the PDC transfer request with a comparison match (see
Section 37.6.3 “PWM Comparison Units” ), by the fields PTRM and PTRCS in the PWM_SCM
register.
Method 1: Manual write of duty-cycle values and manual trigger of the update
In this mode, the update of the period value, the duty-cycle values and the dead-time values
must be done by writing in their respective update registers with the CPU (respectively
PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK of the “PWM Sync Channels
Update Control Register” (PWM_SCUC) which allows to update synchronously (at the same
PWM period) the synchronous channels:
• If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the
synchronous channels.
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is
read 0.
Table 37-5. Summary of the Update of Registers of Synchronous Channels
UPDM=0 UPDM=1 UPDM=2
Period Value
(
PWM_CPRDUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to 1
Dead-Time Values
(
PWM_DTUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to 1
Duty-Cycle Values
(
PWM_CDTYUPDx)
Write by the CPU Write by the CPU Write by the PDC
Update is triggered at the next
PWM period as soon as the bit
UPDULOCK is set to 1
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR
Update Period Value
(
PWM_SCUPUPD)
Not applicable Write by the CPU
Not applicable
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR