iv
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Cortex M Cache Controller (CMCC) User Interface ......................................358
Cyclic Redundancy Check Calculation Unit (CRCCU) ..................... 369
Transfer Control Registers Memory Mapping ................................................373
Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface ..........377
SAM4S Boot Program .......................................................................... 393
Hardware and Software Constraints ..............................................................393
Bus Matrix (MATRIX) ........................................................................... 399
Special Bus Granting Techniques .................................................................400
Bus Matrix (MATRIX) User Interface .............................................................404
Static Memory Controller (SMC) ......................................................... 413
25.2
Embedded Characteristics ............................................................................413
25.7
Summary of Contents for SAM4S Series
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