62
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Where:
-
Means that the memory system does not guarantee the ordering of the accesses.
<
Means that accesses are observed in program order, that is, A1 is always observed
before A2.
11.4.2.3
Behavior of Memory Accesses
The behavior of accesses to each region in the memory map is:
Note:
1. See
“Memory Regions, Types and Attributes”
for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see
“Memory Protection Unit (MPU)”
Additional Memory Access Constraints For Shared Memory
When a system includes shared memory, some memory regions have additional access con-
straints, and some regions are subdivided, as
shows:
Table 11-4.
Memory Access Behavior
Address Range
Memory Region
Memory
Type
XN
Description
0x00000000 - 0x1FFFFFFF
Code
Normal
-
Executable region for program code. Data can also be
put here.
0x20000000 - 0x3FFFFFFF
SRAM
Normal
-
Executable region for data. Code can also be put here.
This region includes bit band and bit band alias areas,
see
0x40000000 - 0x5FFFFFFF
Peripheral
Device
XN
This region includes bit band and bit band alias areas,
see
0x60000000 - 0x9FFFFFFF
External RAM
Normal
-
Executable region for data.
0xA0000000 - 0xDFFFFFFF
External device
Device
XN
External Device memory
0xE0000000 - 0xE00FFFFF
Private Peripheral Bus
Strongly-
ordered
XN
This region includes the NVIC, System timer, and
system control block.
0xE0100000 - 0xFFFFFFFF
Reserved
Device
XN
Reserved
Table 11-5.
Memory Region Shareability Policies
Address Range
Memory Region
Memory Type
Shareability
0x00000000-
0x1FFFFFFF
Code
Normal
-
0x20000000-
0x3FFFFFFF
SRAM
Normal
-
0x40000000-
0x5FFFFFFF
Peripheral
Device
-
Summary of Contents for SAM4S Series
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