Atmel SAM4S Series, Preliminary Data Sheet

Page: 688 / 1163

688
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Note that a STOP or a repeated START always follows a NACK.
See Figure 32-25 on page 689 .
32.10.4.2 Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register
Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive
Holding Register). RXRDY is reset when reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED an address dif-
ferent from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set
and SVACC reset.
See Figure 32-26 on page 689 .
32.10.4.3 Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock
synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 32-28 on page 691 and Figure 32-29 on page 692 .
32.10.4.4 General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL
and to decode the new address programming sequence.
See Figure 32-27 on page 690 .
32.10.4.5 PDC
As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT rec-
ommended in SLAVE mode.
32.10.5 Data Transfer
32.10.5.1 Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address
starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direc-
tion of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded
in the TWI_THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 32-25 on page 689 describes the write operation.