Atmel SAM4S Series, Preliminary Data Sheet

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435
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 25-19 shows a read access controlled by NRD, followed by a write access controlled by
NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
Figure 25-19. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
25.11.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, TDF wait states are inserted at the end of the read transfer, so
that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional TDF wait states will be
inserted.
Figure 25-20 , Figure 25-21 and Figure 25-22 illustrate the cases:
• Read access followed by a read access on another chip select,
• Read access followed by a write access on another chip select,
• Read access followed by a write access on the same chip select,
with no TDF optimization.
NCS0
MCK
NRD
NWE
D[7:0]
Read to Write
Wait State
TDF_CYCLES = 6
read access on NCS0 (NRD controlled)
NRD_HOLD= 4
NWE_SETUP= 3
write access on NCS0 (NWE controlled)