144
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Examples
SMMLA
R0, R4, R5, R6
; Multiplies R4 and R5, extracts top 32 bits,
; adds R6, truncates and writes to R0
SMMLAR
R6, R2, R1, R4
; Multiplies R2 and R1, extracts top 32 bits,
; adds R4, rounds and writes to R6
SMMLSR
R3, R6, R2, R7
; Multiplies R6 and R2, extracts top 32 bits,
; subtracts R7, rounds and writes to R3
SMMLS
R4, R5, R3, R8
; Multiplies R5 and R3, extracts top 32 bits,
; subtracts R8, truncates and writes to R4.
11.6.6.8
SMMUL
Signed Most Significant Word Multiply
Syntax
op{R}{cond} Rd, Rn, Rm
where:
Operation
The
SMMUL
instruction interprets the values from
Rn
and
Rm
as two’s complement 32-bit signed
integers. The
SMMUL
instruction:
• Multiplies the values from
Rn
and
Rm
.
• Optionally rounds the result, otherwise truncates the result.
• Writes the most significant signed 32 bits of the result in
Rd
.
Restrictions
In this instruction:
• do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL
R0, R4, R5
; Multiplies R4 and R5, truncates top 32 bits
; and writes to R0
SMULLR
R6, R2
; Multiplies R6 and R2, rounds the top 32 bits
; and writes to R6.
op
is one of:
SMMUL Signed Most Significant Word Multiply
R
is a rounding error flag. If
R
is specified, the result is rounded instead of being
truncated. In this case the constant
0x80000000
is added to the product before the high
word is extracted.
cond
is an optional condition code, see
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Summary of Contents for SAM4S Series
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Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...