Atmel SAM4S Series, Preliminary Data Sheet

Page: 422 / 1163

422
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
25.8.1.3 Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where
address is set on the address bus to the point where address may change. The total read cycle
time is equal to:
NRD_CYCLE = NRD NRD NRD_HOLD
= NCS_RD NCS_RD NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of
Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define
the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time
and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
25.8.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain
active continuously in case of consecutive read cycles in the same memory (see
Figure 25-6 ).
Figure 25-6. No Setup, No Hold on NRD and NCS Read Signals
MCK
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE NRD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_CYCLE NRD_CYCLE
A[23:0]
NCS
NRD
D[7:0]