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8
General Instruction Characteristics
Section 1-1
Addressing Index Registers
Note Make sure that the contents of index registers indicate valid I/O memory
addresses.
Method
Description
Example
Instruction example
Directly
addressing
Index Registers
MOVR(560) moves the PLC memory address of a
word or bit to an Index Register (IR0 to IR15).
(MOVRW(561) moves the PLC memory address of
a timer or counter PV to an Index Register.)
IR0
IR2
MOVR 0010 IR0
Stores the PLC memory address
of CIO 0010 in IR0.
MOVR 000102 IR2
Stores the PLC memory address
of CIO 000102 in IR2.
Indirect
addressing with
Index Registers
Basic opera-
tion (no offset)
The word or bit at the I/O memory
address contained in IR
@
is used
as the operand. Input a comma
before the Index Register to indi-
cate indirect addressing.
(The bit/word designation can be
determined by the instruction or
operand.)
,IR0
,IR1
LD ,IR0
Loads the status of the bit at the
I/O memory address contained in
IR0.
MOV #0001, IR1
Moves #0001 to the word at the
I/O memory address contained in
IR1.
Constant offset
The offset value (–2,048 to
+2,047) is added to the I/O mem-
ory address contained in IR
@
and
the resulting address is used as
the operand.
(The offset is converted to binary
when the instruction is executed.)
+5 ,IR0
+31 ,IR1
LD +5 ,IR0
Adds 5 to the I/O memory
address contained in IR0 and
loads the status of the bit at that
address.
MOV #0001 +31 ,IR1
Adds 31 to the I/O memory
address contained in IR1 and
moves #0001 to the word at that
address.
DR offset
The signed binary content of the
Data Register is added to the I/O
memory address contained in
IR
@
and the resulting address is
used as the operand.
DR0 ,IR0
DR0 ,IR1
LD DR0 ,IR0
Adds the content of DR0 to the
I/O memory address contained in
IR0 and loads the status of the bit
at that address.
MOV #0001 DR0 ,IR1
Adds the content of DR0 to the
I/O memory address contained in
IR1 and moves #0001 to the word
at that address.
Auto-increment
After the I/O memory address is
read from IR
@
, the content of the
Index Register is incremented by
one or two.
Increment by 1:
,R
@
+
Increment by 2:
,IR
@
++
Note Index registers will be incre-
mented when the instruction
is executed even if an error
occurs and the Error Flag
turns ON.
,IR0 + +
,IR1 +
LD ,IR0 + +
Loads the status of the bit at the
I/O memory address contained in
IR0 and then increments the reg-
ister by two.
MOV #0001 ,IR1 +
Moves #0001 to the word at the
I/O memory address contained in
IR1 and then increments the reg-
ister by one.
Auto-decre-
ment
The content of IR
@
is decre-
mented by one or two and then
the I/O memory address in the
register is used as the operand.
Decrement by 1: ,– IR
@
Decrement by 2: ,– –IR
@
Note Index registers will be dec-
remented when the instruc-
tion is executed even if an
error occurs and the Error
Flag turns ON.
, – – IR0
, – IR1
LD , – – IR0
Decrements the content of IR0 by
two and then loads the status of
the bit at that I/O memory
address.
MOV #0001 , – IR1
Decrements the content of IR0 by
one and then moves #0001 to the
word at that I/O memory address.
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...