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Timer and Counter Instructions
Section 3-6
Operand Specifications
Description
When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
PV is reset to the SV and its Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TIMH(015)/TIMHX(551) starts
decrementing the PV. The PV will continue timing down as long as the timer
input remains ON and the timer’s Completion Flag will be turned ON when the
PV reaches 0000.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. To restart the timer, the timer input must be turned OFF and
then ON again or the timer’s PV must be changed to a non-zero value (by
MOV(021), for example).
The following timing chart shows the behavior of the timer’s PV and Comple-
tion Flag when the timer input is turned OFF before the timer times out.
Area
N
S
CIO Area
---
CIO 0000 to CIO 6143
Work Area
---
W000 to W511
Holding Bit Area
---
H000 to H511
Auxiliary Bit Area
---
A000 to A959
Timer Area
0000 to 4095 (decimal)
T0000 to T4095
Counter Area
---
C0000 to C4095
DM Area
---
D00000 to D32767
EM Area without bank
---
E00000 to E32767
EM Area with bank
---
En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM
addresses in binary
---
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
---
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
---
BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers
---
DR0 to DR15
Index Registers
---
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
SV
Timer input
Timer PV
Completion
Flag
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...